A Wet Process To Form Silicon Dioxide Layer For Through Silicon Via Application

Three dimension integrated circuits（3D IC）or packaging has been considered as the most promising way to solve the contradiction between size minimization and function strengthening.The feature size of IC has reached its up limit which means size reduction at 2D level becomes unaffordable.In 3D IC and packaging,the through silicon via（TSV）interconnection method has the maximum integrated ability with the shortest length of connection so that it is recommended as the best solution.In TSV technology,one of the key processes,the forming of insulation layer has not met the requirement.High cost and low quality,especially at silicon vias with high aspect ratio,of insulation layer elaborated by with traditional dry processing method become an obstacle of TSV application.New elaboration method needs to be found to form TSV insulate layers with best compromise of cost and quality.In this article,a wet process method is developed to form silicon dioxide（Si O₂）layer on silicon substrate.The study of this paperwork includes two parts.Firstly instead of forming Si O₂ directly a pre-insulate-layer porous silicon（PS）is made on the silicon substrate by electrochemical etching in the solution which contains HF.The thickness of PS varies linearly with etching time and etching current density which gives a good control of etching process.It is found that the proportion of HF solution brings different morphology PS named as“fence PS”and“sponge PS”elaborated in weak solution and strong solution respectively.The sponge PS is easier oxidized then the fence PS.Secondly the pre-insulate-layer PS is electrochemical oxidized under low voltage to form Si O₂ layer,it is proved that the oxidation of PS begins at the layer top.The breakdown electric field strength is higher than 7.7MV/cm which is potential for real TSV application.At the end of this paper,elaboration of pre-insulate-layer PS is also developed at real silicon vias.It is found that more efforts is needed to reach good conformity especially for silicon vias with small diameter.