Design And Optimization Of High-performance Issue Queue

With the development of large-scale integrated circuit design technology and the innovation of computer architecture,the performance of processors has increased rapidly.In the innovation of computer architecture,Instruction level parallelism is of great significance to the improvement of processor performance.Instruction level parallelism mainly includes pipeline technology,multi-issue technology,and out-of-order execution technology.Pipeline technology improves processor frequency;multi-issue technology enables processors to execute multiple instructions simultaneously through spatial repetition;out-of-order execution eliminates as much as possible the dependency between instructions and improves pipeline efficiency.The issue queue is the key hardware of multi-issue technology and out-of-order execution technology,and it is a key stage in the pipeline,which has a great impact on the performance of out-of-order superscalar processors.Based on the issue queue of the BOOM processor,this paper proposes an optimization scheme for the issue queue.First analyze the structure and organization of the issue queue in detail,and clarify the relationship between the issue queue and other pipeline stages.The issue queue of the BOOM processor uses a position-based issue strategy,a distributed issue queue structure,and a structure that reads registers after the issue stage.Then,based on the structure of the issue queue and the other pipeline stages,an optimization scheme for the issue queue is proposed,which mainly includes the following five optimization points: 1.According to the characteristics of the BOOM processor memory access system,speculative issue mechanism is added to improve the wake-up capability of the issue queue.When the execution result of the LOAD instruction has not been obtained,the relevant operands in the issue queue can be waked-up speculatively.The next cycle determines whether the speculatively issued instruction will continue according to whether the LOAD instruction hit in the cache;2.Optimize the launch selection logic,Add a dedicated issue port and instruction path for jump/branch instructions,and use the branch execution unit as an independent functional unit,increase the priority of the jump/branch instruction in the int issue queue,give priority to the jump/branch instructions that have a greater impact on processor performance;3.Optimize the dispatch logic between rename and issue queue,determine whether the instructions that need to be scheduled every cycle can completely enter each transmission queue,improve the hardware utilization of issue queue and reduce pipeline stalls;4.Optimize the logic of the instructions shift in the issue queue.Set empty and full flags for each issue slot,and calculate the amount of each shift in the issue queue in parallel to eliminate critical paths and increase frequency;5.Optimize the issue selection logic,select multiple sets of instructions that meet the requirements at the same time,and then select the instructions to be issued twice to eliminate the critical path and increase the frequency.Finally,the verification platform and FPGA test prove that the design achieves the expected function points.This design uses the Xilinx Virtex-7 series FPGA VC709 to run the SPEC CPU 2006 for testing.The result show that,tested with the SPECint benchmark train input set,the IPC of the optimized design increased by 3.52%,tested with the SPECfp benchmark train input set,the IPC of the optimized design increased by 2.76%.In the TSMC 28 nm process library,the INT issue queue can reach a frequency of 1.916 GHz,which is 53.28% higher than the original design frequency,the area increased by 5.02%,teh power increased by35.88%.This design can be used for BOOM processors and other RISC-V processors with a similar issue queue structure as BOOM processors,and has certain engineering application value.