Design And Optimization Of Clock Generation Circuit With Spread Spectrum Function

With the development of integrated circuit manufacturing and the continuous reduction of the size of MOS transistor chips the data transmission rate in wired communication is getting faster and faster,bringing serious electromagnetic interference problems that have become a big obstacle to the development of high-speed transmission chips.Among the many solutions to reduce electromagnetic interference,the technique of spread-spectrum modulation from the input clock source has become one of the main technical method by which to optimize the electromagnetic interference problem due to advantages such as efficiency and low production costs.Specifically,the spread-spectrum clock generator based on the charge pump phase-locked loop is favored by designers.The method of spread-spectrum operation of the clock in the form of direct modulation VCO has attracted people's attention because of it`s feasibility and simplicity.The signal is generated by an analog circuit;when the process angle changes,there is a risk that the modulation in this way will exceed the spreading ratios.Therefore,it is necessary to develop a clock generator circuit with stable spreading ratios based on this architecture.Focusing on the issue of inaccurate and controllable spreading ratios,In this thesis will implement the design and optimization of a direct modulation VCO-type spread-spectrum clock generator.In this thesis,modeling and analyze the loop by using Verilog_A.The circuit design based on the SMIC 0.18?m process will be completed,besides,the system functions and performance will also be performed by using Spectre,AMS,and Finesim simulation tools.In order to make the spreading ratios accurate and controllable,while jitter performance of the spread-spectrum clock and the spread-spectrum modulation effect will be taken into considered,the reasons for the unsatisfying modulation effect of this architecture will be analyzed in the thesis.The VCO modulation method by using dual current injection loop filter,while a spread-spectrum feedback control loop that performs negative feedback adjustment on the clock's spread-spectrum ratios will also be introduced to achieve the reduction of electromagnetic interference and accurate control of the spread-spectrum ratios.This design meets the PCIe protocol and can be used as an input clock signal to PCIe bridge chips,PCs,Ethernet and other chips.The spread-spectrum clock generator circuit designed in this thesis can work normally under the environment of power supply voltage of 3.3V±10% and temperature range of-55? to 125?.By using 25 MHz crystal input,the output frequency and spreading ratios through external configuration can be directly selected.There are 16 types of clock signal output modes,including 25 MHz,100MHz,125 MHz,and 200 MHz.The spreading ratios includes ± 0.25%,-0.5%,-0.75% and nonspread spectrum mode.Besides,more signal output modes can be expanded with simple configuration of the registers.The simulation results show that the deterministic jitter is 17.7ps,cycle-to-cycle peak jitter is 8.9ps,cycle-to-cycle RMS jitter is 1.5ps when the 200 MHz clock frequency is output in the non-spread-spectrum mode.And the signal electromagnetic interference intensity is reduced in the spread ratios of-0.5% mode 8.6dbm,cycle-to-cycle peak jitter is 45.8ps,cycle-to-cycle RMS jitter is 8.5ps.