Design And Implementation Of Configuration Memory SEU Tolerant Viterbi Decoders In SRAM Based FPGAs

In many modern communication systems,convolutional encoding of transmitted signals in transmitters and Viterbi decoding of received signals in receivers are often used to ensure the reliability of communication.In which,Viterbi decoding algorithm can effectively correct errors caused by channel noise and other imperfections and it is the key to achieve low bit error rate.Based on different application scenarios,Viterbi decoder can be implemented on SRAM-based Field Programmable Gate Array(SRAM-FPGA)and other processing platforms.However,in some special electromagnetic radiation environments,such as satellite communications,Viterbi decoder based on SRAM-FPGA is vulnerable to radiation or high-energy particle bombardment,resulting in soft errors.Soft errors,such as Single Event Upset(SEU),can damage the configuration memory of Viterbi decoder and affect its normal operation.The SEU may change the function of the circuit,and the fault will persist until the FPGA is reconfigured and the Viterbi decoder is restarted.This makes the protection of configuration memory of Viterbi decoder based on SRAM-FPGA become an important issue.In this paper,firstly,the experiment of fault injection is carried out,and the effect of soft error on the configuration memory of Viterbi decoder based on SRAM-FPGA is studied.On this basis,the types of configuration memory fault of Viterbi decoder caused by SEU and the tolerance capability of Viterbi decoder to these faults are analyzed.Based on this,several alternative fault detection methods are proposed by using the critical parameters of the decoder,and the combination of fault detection methods is used to study the fault detection scheme.Combined with the fault detection scheme,an effective “Duplication with Comparison”(DWC)fault-tolerant design scheme is proposed.Finally,the evaluation results of the DWC scheme show that the DWC fault tolerant scheme can achieve a similar fault tolerance rate with the traditional three mode redundancy fault tolerant scheme at low resource utilization rate.