The Circuit Design Of In-memory Computation Based On Double Word Lines SRAM

In recent years,with the rapid development of technology in the field of artificial intelligence,there are more and more data-intensive and computationally intensive application scenarios.These application scenarios often have the characteristics of high memory accessibility,multiple parallelism,and multiple repetition.The large amount of data and calculation put forward a more severe test to the pursuit of high speed and low power consumption of integrated circuits.However,the bus speed used to transmit data and instructions of traditional von Neumann computing architecture chips limited frequent data exchange between the computing unit and the memory.At the same time,the proportion of energy and time consumed in data transmission is very large.The bottleneck of von Neumann's computing architecture has become increasingly prominent,and the development and application of artificial intelligence are severely restricted.In-memory calculation embeds some logic operations in the memory,performs multi-row or multi-column data reading,computing and saving back operations,in order to reduce the time and power consumption of data transmission between the arithmetic unit and the memory,so the in-memory computing become one of the ways to solve the shortcomings of von Neumann's computing architecture.This article first analyzes the "memory wall" and high power consumption problems faced by the current computing architecture,and introduces the research background of computing in-memory and the current research status in the domestic and overseas.Subsequently,the circuit structure and working principle of Static Random Access Memory(SRAM)are analyzed in detail,and some peripheral circuits of the SRAM module are introduced at the same time.SRAM,which has the characteristics of high speed,low power consumption,and good compatibility,has always been one of the key areas in the research and application of inmemory computing technology.On this basis,several SRAM-based computing in-memory technologies are introduced.Based on the 6T-SRAM cell,this paper proposes a circuit model of double word line memory computing.Under this circuit model,through a separate read port,the circuit has a higher reading static noise tolerance than traditional SRAM circuits.The strategy of using different reference voltages can output the result of complex Boolean logic operation through the sense amplifier.By controlling the input of the word line,the circuit can complete binary content addressing and ternary content addressing operations.Finally,under the 65 nm CMOS process,a 128 × 128(16 kb)storage array was built,and the simulation verification was completed.The circuit was analyzed in terms of power consumption and speed.The simulation results show that,when VDD is 1.2 V,the speeds of the memory logic operation and the binary content addressing operation are 793 MHZ and 813 MHZ,respectively,and the power consumption is 31.4f J/bit and 0.85 f J/bit,respectively.