Research On Key Technologies Of SM9 Identification Cipher Algorithm

With the rapid development of information technology,the confidentiality of information is of paramount importance,and cryptography has also become a powerful guarantee for national information security.SM9 is an identification password standard independently researched and developed by my country and adopted by the State Cryptography Administration in 2016.Pairing is widely used in the application field of Identity-Based Crypto system(IBC)system.Compared with traditional public key cryptography,SM9 based on bilinear pairing has a more complicated mathematical structure and operation process.Therefore,improving the calculation efficiency of bilinear pairing is a key technology to improve the overall performance of SM9.With the goal of improving the calculation efficiency of bilinear pairing,this thesis conducts in-depth research on the Optimal ate bilinear pairing algorithm and calculation process,and proposes an Fp~2-FIOS modular multiplication algorithm to improve the efficiency of bilinear pairing.Based on the analysis of the basic theories and existing algorithms of bilinear pairing,this thesis knows that Quadratic Extension Field(Fp~2)is the basic operation field in bilinear pairing,which improves the computational efficiency of modular multiplication in Fp~2.Improving bilinearity is an effective method for calculation efficiency.Based on the above point of view,this thesis proposes a bilinear pair-oriented Fp~2-FIOS modular multiplication algorithm,which can be used to calculate modular multiplications of the form(A·B+C·D)mod P;this algorithm reduces Calculate the amount of redundancy;and design two parallel scheduling methods for the algorithm.The algorithm can be used not only for SM9,but also for IBC schemes within the range of other parameters.Based on the Fp~2-FIOS algorithm,the modular multiplication operation unit and the bilinear pair operation unit are designed and implemented,and verified.According to different application requirements,this thesis proposes two modular multiplication architectures based on Fp~2-FIOS,and uses the modular multiplication architecture to design a bilinear pair operation unit and use SM9standard parameter verification.Under TSMC 55nm standard process conditions,the implementation and performance analysis of modular multiplication architectures and bilinear arithmetic units with different multiplication word lengths are carried out.The results show that when the multiplication word length is 64 bits,the highest operating frequency of the two modular multiplication architectures can reach2.0GHz,and the area is 110K and 139K equivalent gates,respectively.It takes15.5ns and 12.0ns to complete a modular multiplication.Compared with the existing literature,the proposed architecture is superior to the same type of modular multiplication design in terms of performance indicators such as one-time modular multiplication time,maximum operating frequency and area-time product.The operating frequency of the bilinear pairing unit is 500MHz,and it only needs 97,824clock cycles to complete the 128-bit security level Optimal-ate pair calculation,the required time is 0.186ms,and the area is 850K equivalent gate.Through comparison,it can be seen that the bilinear pair operation unit adopting Fp~2-FIOS algorithm has obvious advantages in operation time compared with the same type of design.