Experimental Process Of 12inch Semiconductor Grade Czochralski Silicon Crystal

Semiconductor silicon which is wildly applied in integrated circuit and power devices is the fundamental material of micro electronic industry.The decreasing critical size of integrated circuit demands silicon wafers to be of large diameter and to be defect-free.Presently,12-inch Czochralski silicon wafers are the mainstream material of integrated circuit.The huge demand for 12-inch Czochralski silicon wafers ask for low cost manufacturing.Thus,the developing of 12 inch wafers and the study of crystal production process are of great practical and economical significance.Focusing on production of 12-inch Czochralski silicon wafers,we research the effect of hot-zone design,control parameters and magnetic field on crystal growth in this study.The influence of control parameters on the production of crystal is analyzed by simulation.The shortcomings of high cost,high energy consumption,long experimental period and difficult observation of crystal growth were solved.Under the instruction of simulation,12-inch dislocation-free crystal was prepared by32-inch hot zone,and the melt level distance and pulling speed range suitable for high-quality silicon crystal growth are obtained which filled the blank of domestic12-inch semiconductor crystal production.Four probes method was used to measure the resistivity of the crystal.The study of the crystal resistivity distribution is not only demand of the following application in integrated circuit,but also shows the radial uniformity of the rods.The oxygen content distribution of the crystal was measured by FTIR(Fourier Transform Infra-Red),which provided a guidance direction for driving the mechanical strength and the oxygen precipitates distribution to be more uniform,and also provided reference for the growing of larger size crystal.Through analysis of the copper decoration method,the micro defect can be transformed to macro patterns.Thus,crystal defect types can be confirmed in the process of crystal analysis and evaluation instead of the confirm after the polish wafer defects analysis in the past.Advance confirm of crystal defect types,which not only saves a lot of processing cost and time,but also provides strong support for process adjustment in time and continuously.Further more,insertion defect can be confirmed,which can avoid the potential risk of yield loss in the following integrated circuit process.Through analysis of the copper decoration method and defects detector results,confirmed the size and quantity of COP corresponding to different defects of copper decoration,according to the requirements of the integrated circuit,matching the corresponding crystal of defects type.