Research On Heart Sound Classification Based On Convolutional Recurrent Neural Network And Hardware Acceleration Method

Congenital heart disease seriously endangers the health of young children in China.Heart sound auscultation is the simplest and most effective method in the initial diagnosis of congenital heart disease,but it relies heavily on the clinical experience and examination skills of physicians.This study aims to apply an artificial intelligence-based heart sound classification system to the initial diagnosis of precocious heart disease,and provide timely and effective machine-aided diagnostic advice to physicians with the help of deep learning,hardware acceleration,and edge computing,so as to effectively solve the situation of missed diagnosis and misdiagnosis caused by inexperience or subjective judgment of primary care physicians in precocious heart disease screening.In this paper,we design a convolutional recurrent neural network gas pedal based on APSo C for heart sound classification system,and the convolutional layer acceleration module of this gas pedal can be dynamically configured according to different network structures.In this paper,we have done the following research work.1.A dynamically configurable convolutional layer acceleration module with high compatibility is designed based on APSo C.The CRNN network structure used in the automatic classification model of heart sounds is analyzed,and the hardware architecture is designed to fit all the convolutional layers in the model according to the maximum number of input and output channels,input and output feature map sizes,and the number and size of convolutional kernels in the network structure.The parallelism is optimized in three dimensions: input channel parallelism,output channel parallelism,and intraconvolutional core parallelism,and the acceleration module is optimized by Int16 fixedpoint quantization,input channel interleaved cache,sliding window mechanism,and HLS instructions.2.According to the logic of LSTM forward computation algorithm,the hardware acceleration modules corresponding to vector matrix operation,activation function operation and point-by-point operation are designed in turn.The data bit width is compressed by Int16 fixed-point quantization,and the slice cache weight matrix is used to optimize the storage occupation of the LSTM acceleration module,and the sigmoid and tanh in the activation function module are fitted with segmentation functions to improve the computational efficiency.3.The dual DMA mechanism and AXI4-Stream Switch module are designed to optimize the data flow and to reuse the convolutional acceleration module.In view of the large size of the convolutional recurrent neural network parameters,it is not possible to store all the parameters into the on-chip cache at one time,so a dual DMA mechanism is designed to transfer the weight matrices of the convolutional and LSTM layers separately.In addition,the AXI4-Stream Switch module is used to optimize the data flow direction,so that different acceleration modules can be scheduled according to different network structures to achieve the target model,which saves hardware resources and reduces the model loading latency at the same time.The CRNN hardware gas pedal is more flexible after optimizing the data flow direction,and can schedule both the convolutional and LSTM layer accelerators to implement CRNN,or only the convolutional layer accelerator to implement CNN with different network structures.The Xilinx Zynq-7020 development board was used as the implementation platform to build the acceleration system.The experimental results show that the CRNN accelerator designed in this paper can achieve 9.403 times the acceleration effect of the i7-9750 H CPU,but its power consumption is only 1.91% of that of the GTX 1660 Ti GPU,so this hardware accelerator The hardware accelerator is already worthy of practical application.