Research On TPC Decoding Algorithm Based On Probability Calculation And FPGA Design

With the continuous development of modern medical technology,a variety of medical devices have emerged,among which wearable devices that can be used for remote monitoring of health data have been used in large numbers,so the Wireless Body Area Network(Wireless Body Area Network,WBAN)technology,which can provide real-time health monitoring for patients and assist in the diagnosis of many diseases,has attracted extensive research.At the same time,the rapid development of modern wireless communication and the miniaturization of medical electronic devices have promoted the development and application of wireless body area network technology.The data reliability of medical equipment is determined by the data rate,low data rate is high BER,high data rate is low BER,the data rate in the application of medical wireless body area network is not very high,so the decoding algorithm in the channel needs to have good decoding performance.Turbo Product Code(Turbo Product Code)can perform well by applying iterative decoding method,and the commonly used decoding algorithm is Pyndiah-Chase-Ⅱ algorithm,but Pyndiah-Chase-Ⅱ algorithm involves a lot of sorting operations in the process of finding the most unreliable input bit position and the shortest Euclidean distance code word,the complex branch structure and storage scheduling make it unfavorable to be implemented with FPGA or integrated circuit hardware.So a TPC decoding algorithm based on probability calculation(Stochastic-TPC decoding algorithm)is proposed for the above problem,the Stochastic-TPC decoding algorithm consists of five layers: input layer,random bit stream generation layer,BCH hard decision layer,BCH&CRC check layer,and output layer.Stochastic-BCH decoding algorithm is used for the sub-code algorithm of Stochastic-TPC decoding algorithm,MATLAB is used to simulate and analyze the decoding performance of Pyndiah-Chase-Ⅱ decoding algorithm,Stochastic-BCH decoding algorithm,and Stochastic-TPC decoding algorithm,and the simulation results show that the Stochastic-TPC decoding algorithm can achieve(random bit stream length L=512)or even outperform the Pyndiah-Chase-Ⅱ decoding algorithm(random bit stream length L=1024).Finally,the Stochastic-BCH decoding algorithm and Stochastic-TPC decoding algorithm are designed in logic circuits and simulated in modelsim.In terms of logic circuit implementation,the BCH hard decision layer is implemented by means of lookup tables,the BCH&CRC layer can be accomplished by using basic heterogeneous gates,the random bit stream generation layer is implemented by comparators,and the input-output layer is mainly a register set.