Implementation Of ECG Detection Algorithm Based On FPGA

Heart disease is a prevalent global health issue and a significant contributor to mortality.The Electrocardiogram(ECG)provides a wealth of physiological information pertaining to the heart,and its analysis plays a crucial role in medical diagnosis.Portable ECG detection devices offer the convenience of monitoring ECG at any time,and can be used as a diagnostic tool to aid in the prevention and treatment of heart disease.However,existing portable ECG detection devices typically lack an intelligent hardware module for detecting abnormal ECG signals.Therefore,the hardware implementation of the ECG signal detection algorithm allows the construction of hardware modules for the detection of abnormal ECG signals.Then,the designed hardware modules are embedded into current portable ECG detection device to ensure that the device can detect abnormal ECG signals in real time.This article presents a novel intelligent logic chip IP core and system for processing Electrocardiogram signals related to four types of cardiac arrhythmia.The system has been specifically designed and analyzed to optimize its circuit architecture,accuracy,throughput,hardware resource utilization,dynamic power consumption,and software algorithm reference models.The system consists of two main components.Section(1)is the R-wave location pre-processing section based on differential threshold algorithm.And section(2)is the feature training and inference section based on Convolutional Neural Network(CNN).For the section(1),an improved R-wave threshold location algorithm is proposed based on the existing differential threshold algorithm.The proposed algorithm calculates the maximum differential mean of the 1500 ECG training samples data and processes it as a threshold.Then,using the threshold comparison module to infer the pre-screened candidate R waves.Further,secondary post-screened is performed by dynamic adjustment of the heart rate cycle interval,and the accurate location of the R waves can be obtained.For the section(2),the set which is collected from R-wave peak neighborhood points generated by the differential threshold method,i.e.,the downsampling ECG R-wave data set,is fed into the CNN for training and inferring.Referring to the Le Net-5 model,this thesis has made improvements in the network structure and achieved the transformation from the original two-dimensional data input network model to a one-dimensional sequential data network model.The CNN network structure consists of six layers: the input layer,the middle hidden layer which is composed of three convolution layers,and the last two fully connected layers.The R-wave data set from the Section(1)is divided into two sets:training data set and validation data set,and the improved CNN network is pre-trained using the training data set.By setting the learning rate and type of the training optimizer in advance,adjusting the size of stride,input sequence,convolution kernel,number of nodes in the fully connected layer,and analyzing the iterative training times and full connection layer scoring results,a compromise between fast convergence and output result accuracy is achieved.The detection rate of the CNN network model is found to be approximately 99.58%.This thesis presents a hardware implementation of the R-wave detection algorithm part and the CNN classification algorithm part based on FPGA.Firstly,for the R-wave detection algorithm module,a circuit structure with local pipeline and global asynchronous is proposed to achieve a balance between throughput performance and dynamic power consumption.The implementation of the logic circuit is carried out.In order to meet the throughput requirement,this thesis calculates the speed statistics of the database electrocardiogram heart rate and the clock cycle of the R-wave positioning module,and gives the minimum clock frequency.This clock frequency can be adjusted to adapt to different scenarios of electrocardiogram disease treatments.The iterative comparison module in the R-wave localization section utilizes time-division multiplexing technology to reduce the resource consumption caused by the hardware comparators.Secondly,the CNN hardware module implements pruning and simplification derived from the six-layer CNN model in the software section,and achieved forward inference based on the reference model.The simplified CNN network model achieves an accuracy of about 98.3% in the software environment.In this thesis,we analyzes and designs the key modules of a hardware implementation of the CNN classification model with pipeline structure circuit to achieve a balanced design of low resource consumption,sufficient inference accuracy and speed.The goal is to achieve accurate and effective multi-classification of arrhythmia symptoms.These modules include the circuit design of the convolutional array,the Re LU activation function,the average pooling circuit,the fully connected layer,and the Soft Max function.Finally,the designed R-wave detection IP core and CNN-IP can be conveniently used to construct intelligent hardware circuits,and realize portable wearable AI chips and systems.