Research And Design Of Sampling And Compression Chip For ECG Signals

In recent years,the mortality rate caused by cardiovascular diseases has continued to rise,and the patients are getting younger.Monitoring real-time electrocardiogram(ECG)signals can help doctors detect and treat diseases during the incubation period,thereby decreasing unnecessary casualties.With the increasing awareness of public health,the demand for ECG monitoring for disease prevention is also increasing.Limited by the battery capacity,the data transmission of ECG monitoring devices is under great pressure of power consumption.The compressed sensing(CS)algorithm can reconstruct original signals with only a small amount of data,making the low-cost ECG monitoring possible.By compressing the sampled signals,the amount of transmitted data can be effectively reduced,hence reducing the power consumption of ECG monitoring devices.However,with the decreasing semiconductor process nodes,the power consumption and heat per unit area of the chip increase dramatically.Therefore,designing low-power ECG signal sampling and compression chips has currently become a hot research topic.This thesis designs and implements a low-power sampling and compression chip based on the CS algorithm to process ECG signals.According to the function requirements,the whole process is completed,including the algorithm design,system design,register transfer level design,gate level netlist design,and physical layout design of the chip.The chip is taped-out and verified,and the iterative optimization design is performed based on test results.The main research contents of this thesis are as follows.1.The key modules of the CS algorithm are studied and designed.Parameters such as the sampling frequency and compression ratio of ECG signals and the dimensions of original and compressed signals are determined by algorithm simulation.The sources of power consumption of CMOS digital integrated circuits are described,and the low power consumption design strategies and implementations are analyzed and applied to the sampling and compression chip in this thesis.2.The system architecture is designed.An analog to digital converter(ADC)and a CS compression circuit are integrated to realize the sampling and compression of ECG signals.A12-bit ADC with high precision and low power consumption is adopted,and the design and simulation of the CS compression circuit are realized by modules.The constructed matrix has good compression and reconstruction performance and only consumes a few hardware resources.The matrix sequence is analyzed and calculated to determine the minimum number of bits of compressed data,avoiding the redundancy of register units.The data output is synchronized with the compression,and the operation is turned off to a low-power consumption state during the idle phase of the transmission.After verifying that the functions of each module are correct,a mixed digital-analog simulation is performed on the sampling and compression chip.3.The design and verification of the chip layout are completed in a 55 nm CMOS process.The relevant files of ADC are extracted for integration with the CS compression circuit.The logic synthesis and physical implementation of the chip are performed,and various strategies are adopted to reduce the hardware consumption of the chip.The chip area is 0.265 mm~2,including 0.139 mm~2 of the I/O units and 0.099 mm~2 of the core.In the core,the ADC occupies0.011 mm~2,and the CS compression circuit occupies the remaining 0.088 mm~2.The power consumption of the chip is 2.499μW,of which the I/O units,ADC and CS compression circuit consume 0.988μW,0.214μW and 1.294μW,respectively.4.The designed chip is taped out,and a verification system is built for functional testing and performance evaluation.The chip realizes the sampling and compression of ECG signals successfully,and the data reconstruction is completed on the upper computer.The measured power consumption of the I/O units,ADC and CS compression circuit is 1.155μW,0.229μW,and 1.461μW,respectively.The total power consumption of the chip is 2.845μW.Compared with the simulation results,the experiment results fall in a normal range with small variations.5.Finally,the power consumption results of the chip are analyzed,and the modules with high power consumption are optimized.An approximate calculation method is designed by dividing the matrix compression into high-bit accurate calculation inside the chip and low-bit approximate calculation outside the chip.By designing the timing,pulse latches are used to store the compressed data.The layout is rearranged to maximize the resource utilization of the core.Although the total area of the chip does not change,the core area is only 0.042 mm~2,showing a significant reduction of 57.6%.The total power consumption of the chip is 2.165μW with a reduction of 13.4%.In summary,this thesis designs a sampling and compression chip for ECG signals,which can achieve effective compression and reliable reconstruction of data with the obvious advantage of low power consumption.Various optimization strategies with good versatility are adopted in the whole chip design flow.