Timed automata - Globe Thesis

Keyword [Timed automata] Result: 21 - 40 \| Page: 2 of 3
21.	Modeling And Verification Of ZC Subsystem Based On Timed Automata
22.	Formal Modeling Of UPPAAL Based ETCS-1/ETCS-NTC Level Transition
23.	Modeling Analysis And Verification Of Temporary Speed Restriction Server In High Speed Railway Train Control System Based On Timed Automata
24.	Modeling And Verification Of RBC Control Train Scene Based On Timed Automata
25.	Modeling And Verification Of Complex Scenarios Of Autonomous Chinese Train Control System Level 3
26.	Modeling And Verification Of Operational Scenario Of Train Control System Based On Train To Train Communication
27.	Modeling And Verification Of Movement Authority Based On Timed Auomata
28.	Model Based Safety Testing Method For High-speed Train Control System
29.	Mutation TAIO-Based Test And Evaluation Of Safety Function For New Train Control System
30.	Research On Automatic Generation Method Of Test Sequences For CBTC Zone Controller Based On Model
31.	Modeling And Verification Of Regional Data Center For CTCS-1 Train Control System Based On SysML And Timed Automata
32.	Research On Modeling And Verification Of Train-centric Interlocking Control
33.	Modeling Analysis And Implementation Of RBC Handover Based On Timed Automata
34.	Research And Verification Of Moving Block Function Of VBTC System Based On Timed Automata
35.	Research On Formal Analysis And Fault Diagnosis Method Of Temporary Speed Restriction Of Train Control System
36.	Research On Safety Analysis Method Of Airborne Display System Based On The STAMP Theory
37.	The Construction And Application Of Data Verification Model Of Train Control System Based On Timed Automata
38.	Search-Based Functional And Temporal Testing For The Onboard Interlocking Software Of The New Train Control System
39.	Formal Modeling And Verification Of Section Occupancy Logic Check Based On Model Checking
40.	Research On Risk Coupling Analysis Method For Temporary Speed Restriction Operation Scenarios Of The Train Control System Based On STAMP And Timed Automata
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