Keyword [Delay-locked-loop] Result: 41 - 60 | Page: 3 of 4 41.  Design Of A High-precision Time-to-Digital Converter Based On DLL Control 42.  Design Of Hybrid Time-to-Digital Converter Based On Residual Time Amplification 43.  Design Of A Low Jitter Delay Locked Loop Circuit For TDC 44.  Design And Realization Of DS Spread Spectrum Communication System Based On Two-Stage Acquisition 45.  Study And Design Of Multiplying Delay-locked Loop 46.  Active Analog Delay And Delay Locked Loop 47.  Research And Design Of High Precision Multi Phase Clock Generator 48.  The Radiation-harden Design Of Master-slave DLL For DDR3 SDRAM PHY 49.  Design Of A Clock And Data Recovery Circuit Based On A Delay-and Phase-Locked Loop 50.  Design Of A Low-jitter Delay Locked Loop Circuit For TDC 51.  Research On Wall Clutter Suppression Method For Spread Spectrum Through-The-Wall Radar 52.  Implementation Of High-Precision And Wide-Range Time-to-Digital Converter 53.  Simulation And Design Of A Multilevel Interpolation TDC Based On DLLs 54.  Research And Design Of All-digital Delay-locked Loop Based On FPGA 55.  Design Of A Multiplying Delay-locked Loop Circuit For TDC 56.  Design Of Delay Locked Loop Based On Active Delay Cell 57.  Research And Design Of A Programmable Digital Delay Locked Loop 58.  Research And Design Of Delay Locked Loops For Clock Generator 59.  A Master-slave Delay Locked Loop With Low Jitter Applied To TDC 60.  The Design And Implementation Of A Clock Generator Based On DLL   <<First  <Prev  Next>  Last>>  Jump to

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