Digital Phase-locked Loop - Globe Thesis

Keyword [Digital Phase-locked Loop] Result: 101 - 120 \| Page: 6 of 6
101.	A low complexity digital phase-locked loop based frequency synthesizer
102.	Digital phase-locked loop design for naval applications
103.	A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution
104.	A wide band adaptive all digital phase locked loop with self jitter measurement and calibration
105.	A Low Power CMOS Design of An All Digital Phase Locked Loop
106.	Implementation of DSP carrier recovery using all-digital phase-locked loop with vector rotation techniques for high-speed 8-PSK modems
107.	Design Of Low Phase Noise CMOS Digital Phase-locked Loop
108.	An All Digital Phase Locked Loop For Image Sensors
109.	Designs Of Frequency Dividers In Millimeter-Wave All-Digital Phase Locked Loops
110.	Design And Research Of High-Performance And Low-power All Digital Phase-locked Loop
111.	Research On Frequency Locking Technology Based On Digital Linear Phase Comparison
112.	The Core Chip Design Of Fast Locked All Digital Phase-locked Loop
113.	Carrier Frequency Measurement Of Modulated Signal Based On Carrier Synchronization
114.	Design And Implementation Of High Precision Time Base Calibrator Based On Digital Phase Locked Loop
115.	Research And Design Of TDC And AFC In Phase-Locked Loop
116.	Development And Performance Evaluation Of Low-phase-noise High-stability Fast-locking Phase-locked Loop
117.	Research On Sparse Channel Equalization Algorithm In Underwater Acoustic Communication
118.	Design Of All Digital Phase Lock Loop For SoC Clock Generation
119.	The Design Of Low-power All Digital Phase-Locked Loop Used In CMOS Image Sensor
120.	Research And Design Of A CMOS Millimeter-Wave Low-Phase-Noise Cascaded PLL Frequency Synthesizer
<<First <Prev Next> Last>> Jump to