Performance Study For Digital Protection Systems Based On IEC 61850 Process Bus Architecture

Digital protection systems based on process bus architecture play a very important role in the application of Digital Substation Automation System (SAS); their performance directly affects power system security and stability. Process bus-based digital protection system generally consists of Conventional/Non-conventional Instrument Transformer (NCIT), Merging Unit (MU), Ethernet Switch, Protective IED (Intelligent Electronic Device), Time Synchronisation Source, Breaker Controller, etc. The process bus defined in IEC 61850-9-2 works as a bridge between primary and secondary systems. It enables the use of a digital link between current/voltage transformers or merging units (MUs) and bay devices such as protective relays, bay controllers or meters. Different process bus architectures and time synchronisation accuracy of process bus communication have great impact on the performance of digital protection systems, the problems caused by saturation of conventional CT for current differential protections which may operate in conjunction with NCIT must be solved as well. Consequently, it is of vital theoretical and practical importance to study the impact and solutions of the aforementioned factors on the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations. The work summarised in this thesis is also the important content of the project entitled "Protection Performance Study for Secondary Systems with IEC61850 Process Bus Architecture". This project is co-funded by the National Grid Company, U.K., Areva T&D, France, Scottish Power, U.K., Scottish and Southern Energy, U.K. etc and finished by the author in the National Grid Power System Research Centre (NGPSRC) at The University of Manchester.By utilising the minimal tie sets method, sensitivity analysis, the third order difference method and some statistical tools, the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations under various conditions are evaluated and solutions are given. Novel performance testing schemes for the digital protection systems are developed and applied in the project, a CT saturation detection algorithm for use in current differential protection is proposed as well. The innovative achievements and main works of the thesis are as follows:1,Six alternative digital protection system models are proposed based on process bus architecture. Reliability block diagrams are built to assess the functionality of each system and system reliability is calculated using the minimal tie sets method. Sensitivity analysis is carried out on the results to obtain the optimal system architecture and priority ranking of devices.There are four types of general protection system architectures based on process bus:star topology, bus topology, ring topology and mesh topology. The choices of different process bus architectures affect the reliability of protection systems directly. By analysing the pros and cons of different architectures and evaluating the proposed process bus solutions of world-leading manufactures, generic process bus architecture, double busbar substation process bus architecture and mesh substation process bus architecture are designed for NG substations. Six alternative process bus based protection system models are proposed from a component redundancy perspective. The functionality of each system is assessed using reliability block diagrams based on a success-oriented network. System reliability is calculated using the minimal tie sets method determined by the connection matrix. The input data used to calculate the system reliability are based mainly on engineers'experience and judgement rather than on a systematic measurement and collection process. Sensitivity analysis is used to determine the sensitivity of the results to variations in this input data. It was carried out using two approaches; one highlights those components with the greatest impact on system reliability and the other the importance of the task performed by each component in terms of how it affects the functionality of the system. This type of sensitivity approach is useful, not only to determine which components are likely to contribute most to an increase in system performance if their reliabilities are improved, but also to devise ways in which the architecture of the system can be modified to reduce the dominating effect of certain components on the system performance. The results and conclusions can assist both utilities and manufacturers in understanding alternative IEC 61850 process bus architectures and how they affect the performance of protection systems, so that educated and substantiated decisions can be made regarding system design, implementation and maintenance.2,Considering the 1μs time synchronisation accuracy requirements of the Sampled Values transmitted via process bus, three alternative time synchronisation scenarios of MU for different applications in digital protection systems are proposed. They are designed for systems with the characteristics like:parallel line compensation where the synchronisation is between two independent MUs located in two bays; the bay device has a local sampling of conventional CT and VT to be synchronised with the data of the MU or via a technique which time correlates the output to the sampled input data and distributed busbar protection respectively. A "Ping-Pong" principle based synchronisation algorithm applied to a decentralised busbar protection scheme and a differential line protection scheme is also proposed. The time offset between merging units (MUs) and the phase difference of the sampled values (SVs) after this synch process are analysed in detail. Prediction techniques are proposed to improve reliability in case of loss of the GPS signal. For the master/slave principle based IEEE 1588 Precision Time Protocol (PTP) standard, master group concept and democratic algorithms are proposed to cope with master clock failure. By introducing the Transparent Clock (TC) concept, RuggedCOM RSG 2288 Ethernet Switches are utilised in the project to ensure the reliability and accuracy of time synchronisation for process level communication.3,Novel performance testing schemes for digital protection systems are developed based on OMICRON test sets and the RTDS (Real Time Digital Simulator). The impact of IEC 61850 on protection testing is investigated; a performance testing scheme supporting IEEE 1588 V2 for process level communication based on OMICRON test set is developed. The scheme can improve the reliability and accuracy of time synchronisation through a redundant time source. This scheme can reduce three GPS antennas and the P594 time synch units compared with the original scheme (five GPS antennas are needed). The gains are simplified wiring, cost reduction and improved time synch reliability and accuracy for SV. Further more, this test scheme can be modified and expanded easily, the Merging Units and protective IEDs can be swapped readily to facilitate compatibility and interoperability tests. All the devices can simply "plug and test" and this demonstrates the advantages of digital protection systems perfectly. Two merging unit testing platforms are developed based on RTDS and the optimal testing device selection criteria can be concluded by comparing the advantages of OMICRON and RTDS based testing schemes.4,Integrated protection systems are developed in the NGPSRC based on Areva MiCOM protective IEDs. The systems are specially designed for a National Grid mesh topology substation and consist of five panels:digital mesh corner protection panel, Feeder local panel (digital), Feeder remote panel (conventional hardwired), digital transformer LV panel and digital transformer HV panel. A set of performance evaluation indices including absolute/relative and compatibility/interoperability indices are defined. It can be used to evaluate system level and independent component performance. System compatibility and interoperability can also be investigated utilising the schemes. Implementation methodology for performance testing of feeder protection and mesh corner busbar protection is proposed and the proposed schemes and methodology can work as a valuable and effective tool to quantitatively evaluate the performance of the novel protection systems.5,CT saturation has impact on the performance of the hardwired current differential protection in Feeder remote panel B. An improved CT saturation detection algorithm is developed based on the third order difference method by utilising the rate of change criteria of the CT secondary induced voltage. The algorithm evaluates the start and end of each saturation period using the "largest modulus series"; this is derived from the third order difference function applied to the secondary current. The ratios of the absolute values of the CT secondary induced voltage are also used as criteria to determine when the CT is saturated to reduce the possibility of false detection due to the effect of noise. The algorithm is validated by implementing it in a DigSILENT model of a typical 110kV network and its associated protection. Simulation results obtained for various case studies indicate that the proposed algorithm successfully detects the start/end of CT saturation. It is a reliable algorithm for use in conjunction with the biased current differential relay and can eliminate the maloperation and delayed operation of the relays caused by CT saturation.