A Study On Reconfigurable Architecture Of Ultrasonic Signal Processing System

The objective of this dissertation is configuration of ultrasonic signal processing system in the field of Non-destructive Test(NDT) based on reconfigurable computer, as well as the architectures design of signal processing algorithms.Chapter one is the introduction. Firstly, related fields of ultrasonic signal processing technology and algorithms, as well as the imaging technologies and system, are introduced. As the variety and complication of methods and algorithms relating to ultrasonic signal processing increasing, better competencies of real-time, working efficiency and flexibility is needed for the performance of ultrasonic signal processing system (USPS). The recently basic ultrasonic processing systems based on personal computer and embedded system are analyzed and the deficiencies of both basic systems on system optimizing are studied. As a common optimizing method, reconfigurable computer(RC) has been introduced into the ultrasonic signal processing system, but systemic research on the application of reconfigurable computer to the system is far from developing, as the recently applications of reconfigurable computer to the system are only used to take the position of simple logic for interfacing different functional units. Aimed at configuration of USPS based on RC, according to the technologies relating RC and ultrasonic signal processing, the research objective and the key studies of the dissertation are confirmed and research content and scheme of the thesis are carried out.Chapter two is research on software/hardware integrating model of reconfigurable architecture to ultrasonic signal processing system. Analyze on methodologies of traditional design and the software/hardware co-design are implemented firstly. According the analyze above and the requirement of an applicable USPS design, two design methods can not make enough contribution to the construction of reconfigurable USPS. As the variety and complication of signal processing algorithm increasing and practically the reconfiguring unit always in coarse grain including a full algorithm implementation, a new software/hardware integration model is proposed. Upon the new model, the basic architecture of the reconfigurable system is further studied, and the basic functional unit model is described, followed by analyze to organization of the functional unit. The control module based on Finite State Machine(FSM) of the functional unit is constructed. In the end of the chapter, application of the software/hardware integrating model in construction of USPS is carried out.Chapter three is study on dynamic task scheduling and configuration of reconfigurable system and applicable architecture of ultrasonic signal algorithm. Tackling the performance degrade due to reconfiguration of multitask on hardware in reconfigurable system, the scheduling and configuration methods are analyzed. In the point of systemic function of reconfiguration, the optimal algorithm based on virtual memory management of computer system is introduced to set up the scheduling and configuration mechanism. Aimed at construction of USPS, the scheduling and configuration are implemented, in association with the flaw feature extraction and pattern recognition in ultrasonic signal processing in NDT.Chapter four is studies on reconfigurable architecture of wavelet lifting scheme and application to ultrasonic signal de-noising. Aimed at applications of wavelet, especially discrete wavelet, to ultrasonic signal de-noising, The VLSI architecture of Mallat algorithm and lifting scheme are analyzed. Compared to Mallat algorithm, the lifting-based scheme need less VLSI resources and can realize the integer arithmetic. According to application of discrete wavelets to ultrasonic signal processing, a lifting architecture of 9/7 wavelet is proposed, as well as the optimization for the architecture is present. In the end of this chapter, the implementation of the 9/7 wavelet architecture in ultrasonic signal de-noising with adaptive wavelet threshold is carried out.Chapter five is the design of reconfigurable ultrasonic signal processing co-system based on PCI interface. Aimed at an applicable system, the sampling and transportation circuits, including the interface of A/D and FIFO, interface of FIFO and data memory, are configured, by using a FIFO as the temporary storage queue for the sampled data. The data transportation strategies based on PCI transporting modes of master writing and slave reading are adapted, and the circuit is designed. Configurations of different FPGA of Altera are discussed. The method of configuration by downloading the configuring data through PCI from PC is designed, as well as the passive serial configuration is present. In the end of this chapter, the architecture of ultrasonic signal processing co-system is constructed.Chapter six is the conclusions and perspectives. In this chapter, conclusions about the dissertation are drawn and studying perspectives are proposed.