Investigation Of Several Issues In The Impact Of VLSI Process Variations

As one of the fastest developing industries, the improvement of semiconductor industry makes it possible to produce VLSI devices with continuous decreasing feature sizes and increasing integration. Nowadays, as many as billions of transistors can be integrated in a single semiconductor chip. The electronic system, used to be implemented by several chips before, can be manufactured by using monolithic integration. This advantage not only improves the performance of devices and circuits, but also decreases the cost of circuit function unit. However as device feature size shrinks to below 65nm, the application of complex technologies and new materials will inevitably introduce stochastic process variations. These process variations directly induce significant deviation between the key geometric sizes, electrical parameters and their nominal design values, and further lead to the unpredictability of chip performance, increasing difficulty of VLSI design and degradation of circuit yield.To address this issue, this dissertation concentrates on the problem of process variations in VLSI circuits, and researches the impact of process variations at circuit level, chip level and system level respectively. In accordance, three aspects of problems are conducted in this research:the transmission line performance analysis, parameter yield estimation and multi-objective yield optimization, and circuit nominal design optimization. The main research points in this dissertation can be summarized as follows:Firstly, based on the uniform coupled interconnects model, the lumped circuit for interconnects is analyzed by the application of frequency domain method. This method decouples the coupled interconnect model in complex frequency domain and transforms the coupled model into independent interconnects. Then in time domain the estimated expression of crosstalk noise in uniform RLC model is presented, according to the transient response functions of the transformed independent interconnects. The effectiveness of the estimated expression is verified by experimental results. Moreover, the excitation signal in actual circuits is always non-ideal, which has a predominant impact on the analysis of interconnect delay. Considering this impact, an analytical delay model based on coupled RLC interconnect model is presented. For the decoupled interconnects, the two-pole model is combined with the modified one-pole model to simplify the transfer function. The delay expression for coupled interconnects is further proposed by numerical method. Experimental results demonstrate that the analytical method is capable of estimating the delay in coupled RLC interconnects effectively.Secondly, process variations also have an impact on the performance of interconnects. To evaluate this impact, a spectral stochastic method based analysis method for interconnect crosstalk and delay is presented. The suggested method decouples the strongly correlated process variations into orthogonal random variables by principle component analysis. By employing polynomial chaos expression, this work applies two spectral methods, stochastic galerkin method and stochastic collocation method, to estimate the crosstalk and delay in coupled transmission lines. A finite representation of interconnect crosstalk and delay can be further obtained by complex approximation method and numerical method. Furthermore, considering the parasitic coupling effect of multi-interconnects, the stochastic model for multi-interconnects is established. Based on this stochastic model, the delay is estimated by spectrum domain stochastic method and the delay expression in time domain can be finally derived.Thirdly, considering the impact of process variations on VLSI parameter yield, a chebyshev affine arithmetic based yield estimation approach is proposed. Under the assumption of unknown relationships among process variations, this technique predicts the CDF (Cumulative Distribution Function) bounds for leakage power and circuit delay respectively, and estimates the leakage power yield and circuit delay yield based on the predicted distributions. Then by using this estimation technique for parametric yield, a yield multi-objective optimization framework is proposed based on the adaptive weighted sum method. This optimization framework regards both timing and power yield as objective functions and solves the power-delay multi-objective optimization problem with AWS method. AWS is helpful in obtaining a set of uniformly distributed pareto-optimal solutions, therefore is capable of providing sufficient trade-off information between power and delay yield. Experimental results demonstrate that the proposed multi-objective framework effectively solves the problem in traditional optimization methods that optimal solution cannot be obtained in the regions where the curvature of pareto surface is insignificant. Consequently the designer can choose the optimal solutions with different emphasis points.Finally, considering the uncertain distribution of process variations, a robustness quantification rmethod for design parameters in both parameter space and performance space is proposed. Starting with the performance constraints in performance space, this proposed technique applies backward mapping and forward mapping to explore the feasible regions in parameter space and performance space respectively, for the purpose of quantifying the robustness of design parameters in both parameter space and performance space. The robustness indexes are computed based on norm distances. Then with the robustness indexes quantified by this new methodology, a design optimization procedure based on surrogate management framework is proposed. Both parameter robustness and performance robustness are taken into account to construct a bi-objective model and find the trade-off between these two robustness metrics by the surrogates.