Research On The Design Techniques Of High-Efficiency, High-Current And High-Integrated Power Chips

With the rapid development of microelectronics and semiconductor process, power management ICs have been widely used in the areas of communication network, computer and automobile electronics. In recent years the development of DC-DC converter shows some new trends such as high efficency, high current and high integration. Following the market trend, this paper focuses on the research of key techniques and circuit architecture in DC-DC buck converters and solving the related technical difficulties. The main work and innovations of this dissertation are as follows.1. Optimization of PWM control architecture to improve the light-load efficiencyA control structure of power-saving mode is presented. At light loads the chip works in fixed peak current mode with standby intervals. It reduces the average quiescent and switching power loss greatly. The circuit realizes high efficiency at full load, extends battery life and suits for portable applications.2. Eliminating the slope compensation effect on load capabilityA new method which can eliminate the slope compensation effect on load capability is introduced. By increasing the clamp voltage and adding a loop to detect and limit the maximum inductor current, the variation of duty cycle would have little effect on peak current and load capability. And the automatic selection of clamp voltage is achieved through digital counters, which solves the slow response speed problem caused by the high clamp voltage.3. Novel current-sensing circuitA novel integrated CMOS current-sensing circuit for buck converter is proposed. The circuit is concise, simple to implement and the power loss is low. Also the achieved sense ratio is almost independent of temperature, model and supply voltage by matching the MOSFETs. Through optimization, response speed is much faster and minimum input voltage is lower. The circuit can achieve little sense ratio and suits for low-voltage and high-current applications.4. Realization of on-chip frequency compensationAn on-chip frequency compensation structure for current mode DC-DC converter is presented. With integrated RC network, it realizes the loop frequency compensation and overcomes the drawback of stability being dependent on load resistance due to the output ceramic capacitor's low ESR, which reduces the pin numbers, saves the PCB space and stabilizes the chip. Also the optimized feedback network makes crossover frequency insensitive to the change of output voltage, improving the load step response further.5. On-chip soft start circuit designTwo kinds of on-chip soft start circuit are illustrated. One is the step soft start method. The inductor current increases gradually with the digital control of clamp voltage in steps. The other is linear soft start method. A narrow pulse signal is generated by oscillator. To get a ramp voltage, on-chip capacitor is charged intermittently by a small constant current source. Multiplex comparator with low power dissipation is designed skillfully to limit the peak current, which avoids the inrush current and achieves soft-start. Both methods are concise and suit for integration.6. Anti-jamming current-sensing circuitAn anti-jamming integrated CMOS current-sensing circuit for buck regulators is presented. Based on the widely-used traditional current-sensing structure, anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit. Also the transient response is faster through the introduction of current offset. The circuit is concise, simple to implement and suits for monolithic muliti-output DC-DC converters and SoC applications with single power supply.7. Build-in testability design for wafer and package testBy controlling the external pins, the chip enters into a special test mode. With multiple uses of the pins, measurements of many electrical characteristics are realized. The proposed method does not need to cooperate with complicated external control structures and suits for wafer and package test, which reduces the complexity in programming and improves test efficiency. The build-in testability design has no effect on normal operation and achieves good accuracy satisfying demands.