Research On Control Architectures, Synchronization And Fault-tolerant Characteristics Of Distributed Power Converters

Power electronics system integration, standardization and modulation are the most significant issues for power electronics developments in this century. The related technologies of distributed power converters or power systems, which are built with power electronics modules by some interconnection method, are the important research focuses. Hence, the distributed converters built with several power electronics basic cells have been studied in this paper, and new characteristics and possible problems of distributed converters have been investigated systematically and particularly.First, the distributed converters built with several power electronics basic cells have been studied in the paper. The characteristics of distributed converters as well as the hardware designs and control methods are presented in detail. Particularly, the topology selection of the basic cell's power stage, the function design of distributed control, the interconnection of basic cells, the communication protocol design and the definition of the data transportation formats are investigated specifically. The distributed power converters play an important role in improving system reliability, shortening design cycle time and decreasing manufacturing cost. The proposed control design methods for distributed power converters are valuable for the further research.Furthermore, the FPGA-based mixed-signal controller with asynchronous over sampling for switch mode converters is investigated in the paper. The proposed control architecture contains a FPGA, a DAC and a comparator, where the FPGA is a control processor that implements DPWM generation and a PID control algorithm. The DAC in conjunction with the comparator operates in two operational modes: one is a conversion mode performing successive approximation A/D conversion, and the other is a modulation mode providing an instant pulse-width modulator in the analog domain. The fast response of this mixed-signal control architecture makes itself close in dynamic behaviour to its analog counterpart. Furthermore, the proposed solution is also effective, since all components used are viable for power electronics integration. Its features and performance are sufficient to promote itself for implementation in many industrial digital control systems.Besides, synchronization effects and performance degradation of the distributed inverters built with several power electronic basic cells controlled with different PWM strategies, are presented in this paper. The paper analyzes the synchronization performance when three kinds of synchronization errors (i.e., carrier synchronization error, reference synchronization error, and sampling synchronization error) exist by a three phase five-level cascaded inverter built with basic cells. All synchronization errors will lead to additional low order carrier sideband harmonics in the phase leg output voltage, and the THD of the phase leg output voltage increases as the synchronization error increases. This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance systematically, as well as detailed synchronization implementation. Meanwhile, the harmonic energy distribution rules of the output voltage with the synchronization errors are derived from the comparisons of theoretical analysis, simulations and experimental results, as well as the conclusions on the performance degradation with the three kinds of errors. It is noticeable that the carrier synchronization error affects the output voltage performance more significantly than the reference synchronization error and the sampling error.Further, the paper presents the performance degradation of a distributed inverter built with several basic cells using a SVPWM strategy. The transfer of the total harmonic energy of the line-to-line output voltage was explicitly analyzed using Fourier analysis and Matlab simulation, when a synchronization error or startup delay exists between two basic cells. The synchronization error leads to baseband low order haromincs, additional carrier sideband harmonics and odd multiples of carrier harmincs in the line-to-line output voltage. The derived conclusions on the harmonics distribution rules with the synchronization error are valuable for practical applications of SVPWM inverters built with basic modules using a distributed control scheme.Finally, this paper focuses on the fault-tolerance potential of multilevel inverters with redundant switching states built with basic cells. The gate signals can be reconfigured according to the failure modes when some of the power devices fail. Balanced line-to-line voltage will be achieved with the proposed method when device failure occurs. Furthermore, the circuit structures can be the same as the general ones and the voltage stress of the devices does not increase. The solutions for PDPWM and PSPWM strategy are discussed in this paper but the concept can be extended to other carrier-based PWM strategies easily. And also the concept provides a new idea for the fault tolerant technology. The proposed method can easily be implemented since the reconfiguration of the PWM strategy can be implemented in software, without extra hardware requirements. Its perfect characteristics enable itself to be widely used in the multilevel converter applications.The validity and accuracy of the theoretical analysis is proven by many simulations and experimental results in each chapter.The work is sponsored by the National Nature Science Foundation of China (50777055).