Research And Implementation Of Ultra-Fast Sampling System Based On Parallel Processing

With the rapid development of modern science and technology, electronic signal in the various applications(such as communication, computer and aerospace) fetures the characteristic of complication and diversification. For example, signal frequency has been increasing, the bandwidth been broadening, the instantaneity been increasing, and non-stationary been going up. An essential data acquisition system(DAS) used to accurately capture these complicated signals puts forward higher requirments on the performance of sampling rate and resolution, and especially, the demand of ultra-fast sampling system(UFSS) featuring tens-of-giga Hertz sampling rare and more than 8bit resolution is increasing remarkably. Analog to digital converter(ADC) is the key component of DAS. However, such high performace ADC based on single core is currently not avaialbe because of the limitation of manufacturing technics and market products. Therefore, to break through this limitation and obtain higher sampling rate and resolution, parallel based time-interleaved ADC(TIADC) technique has been an effective solution for the higher sampling rate DAS to acquire non-repetitive waveforms in real time. But with the increase of sampling frequency, the UFSS shows new parallelized features which propose a new challenge for the system design and implementation.This paper focuses on solving common problem in UFSS with the object of parallel processing method. Several in-depth research points are carried out on parallel sampling technology, system parallel architecture, mismatch error calibration, multiple device data synchronization and parallel trigger position. Finally, they are verified in practical engineering design, and several superior performances are achieved. The main research results are as follows:1) The characteristics of time and frequency domain are analyzed respectively on sampling techniques and parallel mismatch error(PME) of TIADC and FIADC(frequency interleaved ADC). Then, evaluation indexes of sampling performance are provided. Based on the model of paralled data transport in UFSS, interconnection topology model and functional logic partition algorithm are studied for the implementation of parallel data processing among multiple components. Then, a logic partition solution based function synchronization is proposed that is able to make the UFSS data parallel processing implementation more efficicent and more reliable. When the methods of parallel sampling and processing are considered together, a UFSS overall design diagram based on parallel architecture of multiple-converter and multiple-FPGA(MCMP) is finally provided and offers a feasible reference for the implementation of tens-of-giga Hertz sampling sytem.2) Three expressions of parallel mismatch error are established by sampling parameters of reference voltage, input range and resolution digits. Then, the PME source of TIADC system is analyzed in-depth, and the implementation model of PME calibration is refined from existed PME solution. According to the problem that timing error calibaration in existed resolution is difficult to be implemented, a PME time estimation algorithm based on data statistics is proposed, and its performance is evaluated by the parameters of input signal frequency, noise and length of sampled data. Results show that the proposed algorithm is not only of high resolution in the unkown of each channel gain but also of low computational costa and high real time capacity. It is thus easy to be implemented in FPGA, and offers a strong support for the high resolution realization of TIADC systems.3) The existence and root cause of multiple-converter data synchronization(MCS) problem is are analyzed thoroughly. Then, the MCS model of hardware synchronization and data combination sequence is first established. On basis of this model, two sets of reliable resolution on the front-end hardware reset and the back-end detecting identification are proposed respectively: method of hardware synchrous reset and post-detection identification. Also full demonstration and instantiate analysis are performed for their key design parameters. Results show that the proposed solutions are more thoroughness, high reliability and easy to implement. They lay a solid foundation for the futher enhance of ultra-fast TIADC system performance, and offer a feasible design reference for congeneric systems and instruments featuring the MCS property.4) A mixed type method of deserilizer based trigger fast position is proposed in terms of the discussion of analog and digital parallel trigger position method. It is able to simplify the process of trigger position based on parallel data processing, shortern the required processing time for trigger position, and improve system waveform capture rate. Moreover, according to the reqirment of parallel data transport model and storage synchronous controlling in multiple-FPGA systems, a method of delayer based automatic delay regulation is proposed. It can be easy and flexible to solve the synchronization problem of parallel data storage among multiple FPGAs.5) On basis of the analysis and proposed parallel processing methods in this paper, a MCMP parallel structure based 20 GSPS TIADC system and a full-waveform acquisition system of laser pulse are designed and implemented in detail. Subentry item test is peroformed to verify the feasibility and reliability of these methods. Final results demonstrate that, the proposed parallel processing methods have superior performances of high resolution, strong practicability and high reliability. They also offer a solid fundmantation problem for the UFSS design and implementation.