Research On Digital Calibration Technique For Pipeline ADCs

With the rapid development of digital signal processing, the demand for high performance analog to digital converter(ADC) is becoming more and more rigorous. As a representative of ADCs with medium-high resolution and speed, pipeline is one of the most popular ADC architecture and it is most widely used. With the evolution of CMOS technology, the intrinsic line width narrows, to design pipeline ADC with high performance, the design complexity grows and power consumption is also considerable. With the applying of digitally assisted calibration, digital signal processing technology can be utilized to improve the performance of the traditional analog circuit, thus transform performance improvement from analog region to digital region, analog circuit may continuously benefit from the process evolution, so it’s becoming a research hot pot in today’s integrated circuit design.The two major factors hindering the improvement of pipeline ADC performance are resisual amplifier gain error and multiplying digital-to-analog coverter mismatch error. To improve ADC performance, digital calibration techniques are applied. However, there exist problems in some aspects in the present calibration techniqiues, such as high digital hardware cost, extra analog hardware overhead, limited calibration resolution and so on. In this paper, these problems have been studied. The major contribution of the work includes:To emulate the nonideal factors affacting pipline ADC performance, circuit working details and calibration algorithm calibration effects, high level modeling and simulation are necessary. In this paper, a Verilog-A based pipeline ADC digital calibration technique simulation platform is constructed. After circuit design, an actual verification platform is needed to estimate the hardware overheads and power consumption, based on this, a FPGA based testbench is established. These two work can provide universal simulation and verification platform for digital calibration algorithm, thus lay foundation for the following research.To elliviate the high power consumption of pipeline ADCs, open-loop amplifier can be applied as inter-stage residual amplifier. For the high nonlinearity in open-loop amplifier, statistical based digital calibration algorithm is often used. Traditional statistical based digital calibration algorithm usually store nonlinear errors in ROM, and achieve error value through look up table. The problem is ROM causes high design cost and limited calibration range. Based on this, a statistical based calibration algorithm applying piecewise linear interpolation to estimate amplifier nonlinearity is proposed. In this algorithm, statistical characteristic and piecewise linear interpolation are applied to estimate the third order nonlinearity of inter-stage amplifier, and compensate the error codes to the corresponding backend codes of the amplifier output to achieve calibration. Nonlinear error is calculated through piecewise linear interpolation rather than shored in ROM, thus ROM can be saved and calibration overheads can be reduced.To calibrate amplifier nonlinearty and capacitor mismatch in MDAC simultaneously, MDAC transfer function model is needed to be established. In the former similar calibration algorithm, reference ADCs are usually needed to establish MDAC transfer function model, this will cause extra analog circuit design complexity and analog hardware cost. To solve this problem, a statistical algorithm applying MDAC transfer function model is proposed, to estimate and compensate MDAC capacitor mismatch error and inter-stage amplifier nonlinearity. In this algorithm, MDAC transfer model is constructed based on the statical characteristic of input signals, the nonlinear errors is estimated through the aid of the constructed model, and then compensated in the backend stages. By applying of this, no extra reference ADC is needed, analog circuit design complexity and analog hardware cost are lowered. Simulation results showed that, this algorithm can obviously eliminate the affect of amplifier nonlinearity and capacitor mismatch in MDAC, thus ADC linearity can be greatly improved.To ellviate pipeline ADC system power consumption, low gain closed-loop amplifier, Class-AB amplifier and open-loop amplifier can be applied as inter-stage residual amplifier. The nonlinear distortion in these amplifiers are always high and needs to be calibrated through digital calibration. In the former design, deterministic calibration algorithm is applied to calibration Class-AB amplifier nonlinearity through cubic polynomial interpolation, which suffers from low calibration resolution. Based on this, a deterministic calibration algorithm is proposed to calibration open-loop amplifier nonlinearity. In this algorithm, transfer function model most similar to the actual transfer case is chosen as interpolation function. Firstly transfer function model is constructed through test signal, then interpolation operation is achieved, finally the amplifier input codes are estimated by backend codes and the model. Simulation results showed that, this algorithm can greatly improve calibration resolution. To further verify the calibration technic, a 12 bits, 40 MHz sample rate pipeline ADC is designed. In this ADC, circuit design techniques such as no sample and hold circuit, more redundant bits, stage scaling, operational amplifier sharing, open-loop amplifier design are applied, and layout is finished. Simulation results indicate that, after calibration, the performance of ADC can be obviously improved.