A Video Coding Algorithm And Hardware Architecture Based On HEVC

With the continuous improvement of life quality, the demand for high quality multimedia terminal is also rising. In recent years, UHD, 4KTV and other video terminals with Ultra HD and high frame rate continue to emerge, and the video terminal with 8KTV quality will be soon available. The unlimited demand for better and better for high audiovisual quality has brought a great challenge to the video coding technology. HEVC is a new video compression standard, and can meet the code requirements of 4KTV, 8KTV etc. Compared with the H.264 standard, the compression efficiency can be improved by50%–70%, and the complexity increases by 2–4 times. HEVC coding algorithm relies on intensive computation and a high memory bandwidth and, therefore, the design and optimization of HEVC encoding algorithm and the development of real-time coding system of the corresponding hardware are the key technologies soon to be available in the market.Because of its complexity of HEVC coding algorithm, it cannot achieve the HEVC real-time coding tasks above 4K rate with general processor platform, thus requiring to develop special HEVC video coding IC. The current decoding market share of H.264 is above 80%. Considering the market demand of the compatibility code product, it is required that the new terminal be compatible with the coding algorithm of HEVC and H.264. To address the issues raised above, this dissertation focuses on an in-depth analysis of the optimization procedures of a new generation of video coding algorithm and its corresponding hardware system.In this dissertation key algorithms and the hardware implementation of HEVC video coding methods were analyzed to enable the hardware implementation, improvement and optimization of the intra prediction, inter frame prediction and other video coding algorithm, as well as its corresponding hardware architecture and hardware models of RTL-level. The new architecture is compatible with the H.264 standard, and can achieve the video real-time encoding of 7680 × 4320@35.07 fps,condition of I a single reference frame, the search area is [-16,16].The main research work includes:This paper studies the correlation between the intra coding mode of the coding block and the texture features of the coding block, and proposes the intra coding mode selection algorithm based on the coding block direction gradient. In order to reduce the computation time of the extracted texture parameters, this paper uses the characteristic that the adjacent pixels of the image intra frame space has a strong correlation, has the interlaced extraction of the adjacent pixel gradient parameters of the four directions, and on the basis of the parameters, judges whether the current CU has the next partition and estimate the corresponding texture direction. The proposed texture parameter extraction method can be easily implemented in hardware, and can achieve the realization of hardware circuit in the array in the intra prediction residuals calculation without additional new circuits. According to the H.264 code, there is still a need to extract the correlation parameter of the horizontal and vertical directions to assess the current macroblock texture flatness, and select according to the intra frame mode of I16 MB and I4 MB. The experimental results show that the algorithm can effectively reduce the intra prediction computational time, the changes of the video compression quality and the compression ratio are small, but at the same time, the hardware realization cost is less.The paper also studies the correlation between intra prediction cost and the coding block pixel, proposes the intra / inter mode decision optimization algorithm. In the inter prediction process of P/B frame, calculation of the pixel correlation of the coding block needs the intra prediction to estimate the cost of intra prediction. It then compares the value and the matching cost of the inter frame coding block, thereby reducing the redundancy calculation resulting from direct intra prediction computation. Finally, the experiments show that the algorithm can reduce the intra/inter sentence complexity while guaranteeing the quality of video encoding conditions. At the same time, it completes the CU RTL mapping optimization and assesses the hardware realization cost of the calculation through the simulation experiment. The paper also analyzes motion estimation process of HEVC, and proposes the hardware’s friendly parallel motion estimation calculation according to the data paths and the multi-level partitioning problem of the code block in the motion estimation process of HM source code. In order to further improve the convergence speed of motion search function, it carries out the studies on the relationship between the prediction vector accuracy of the current coding block and the matching error function of the current search center point, and based on the relationship, it proposes the adaptive search range adjustment algorithm based on the parallel motion estimation algorithm of the above. It is proved by experiments that the above parallel adaptive range adjustment motion estimation algorithm can be realized when the changes of the video coding quality and compression rate are small, and also proves the algorithm and hardware high efficiency.Finally, the paper has the RTL modeling of the above motion estimation algorithm.For the realization of the dynamic adjustment algorithm in the reference image area in the search process, it puts forward the 1-D systolic array structure that reference pixel data can be transferred at any time in the corresponding register clock in four directions; it also proposes 3×3 cross line fault storage strategy in order to achieve the demand that the transverse and longitudinal data remains unchanged when being inputting into the bandwidth when scanning of the reference pixel. The experimental results show that, compared with that the algorithm of the reference image region size of the traditional search is unchanged and circuit process, this circuit can greatly improve the speed of image motion estimation.At the same time, it ensures the compatibility of the H.264 architecture. In addition, it enhances the processing capability of the integer motion estimation architecture.