Research On Hardware Accelerator For Parallel Monte Carlo Simulation

Monte Carlo methods are widely used in applications of Physics and Economics. With the requirements of more complicated mathematical models and better computational accuracy, Monte Carlo simulations are consuming more and more computing time. And these lead to the demand for the acceleration for Monte Carlo simulations. In some real-time applications such as Financial computing, this has even become a crucial requirement.Compared with other methods, FPGA based Monte Carlo acceleration shows much better performance on speedup, power dissipation and costs. So, it seems to have a much better development prospect. In this thesis, we focus on the key techniques of FPGA based Hardware Accelerators for Parallel Monte Carlo simulations (HAPMC), which includes the FPGA based uniform random number generation, the FPGA based Gaussian random number generation, the FPGA based parallel random number generation and the bit-width optimization of operands in the hardware accelerator. The major contributions of this thesis are:1. a hardware structure called CTRNG (Combined Tausworthe Random Number Generator) is proposed for the generation of uniform random numbers. Compared with other reported structures, CTRNG has much better performance on speed and hardware consumption. The period and bit-width of the generated random numbers by CTRNG are reconfigurable. And this helps to satisfy the requirements of HAPMC when the number of sampling times and the computational accuracy are changed.2. a hardware structure called BMGRNG (Box Muller Gaussian Random Number Generator) is proposed for the generation of Gaussian random numbers. Through the analysis of Side-Effect and utilization of bit-width optimization method, we could use the design requirements for the HAPMC directly to optimize the hardware design of BMGRNG. And this could suit the BMGRNG well to the whole HAPMC, which leads to better hardware performance.3. a hardware structure called MPRNG (Massively Parallel Random Number Generator) is proposed for the generation of parallel random numbers. MPRNG combines the advantages of both Parameterization Method and Leap Ahead Method to generate massively parallel random numbers. Compared with other reported structures, MPRNG has much better performance on speed and parallelization degree. Also, The period and bit-width of the generated random numbers by MPRNG are reconfigurable. And this helps to satisfy the requirements of HAPMC when the number of sampling times and the computational accuracy are changed.4."Extreme Value Method"and"Sophisticated Static Error Analysis Method"are proposed for the bit-width optimization. What's new here is that the complex Combinatorial Optimization Algorithms are not necessary for the bit-width optimization anymore. Because, by the two methods above, there are only two operands left for bit-width optimization process every time, and we could just use exhaustive method to solve this problem. And this simplifies the design procedure very much.5. a hardware architecture of HAPMC is proposed. And together with the above hardware structures proposed, we implement 320 Monte Carlo hard cores on MAXWELL and acquire very good computing performance.The experiment results show that the structures proposed in this thesis help a lot with the design of HAPMC.