| With the ever-growing systems of battery-powered portable electronic equipments, the problem with battery life has drawn more and more attentions. Presently, the growing speed of the battery capacity is much lower than that of the system power dissipation. Therefore, high-performance DC-DC converters are still the first choice for system designers to increase the battery life. Taking into account the system power dissipation, PCB volume, performance, and cost, modern DC-DC converters are expected to exhibit high efficiency, low harmonic interference, and fast transient response. Based on these requirements, different state-of-the-art techniques are compared in this dissertation, and a low-power fast-transient-response buck DC-DC converter with perfect harmonic suppression under a wider load range is designed.Firstly, different types of power converters including low-dropout regulator (LDO), charge pump or switched-capacitor converter, and DC-DC converter are discussed and compared, especially the operation mode, modulation type, control technique, and output harmonic interference of DC—DC converters.Secondly, the dissertation gives a detailed loss analysis of a buck DC-DC converter under continuous-conduction mode (CCM) and discontinuous-conduction mode (DCM), respectively. The loss sources include the conduction loss of power MOSFET, the charging and discharging loss of parasitic capacitors, the conduction loss of body diode, the switching loss, the conduction loss of inductor parasitic resistor (DCR), the conduction loss of capacitor parasitic resistor (ESR), the loss from output ripple voltage, and the loss from parasitic inductor of PCB wire. The proportion of each loss is achieved by numeracial calculation under CCM and DCM, respectively, which helps to implement efficiency optimization of the converter.After that, a DC-DC system based on a 3rd-order Sigma-Delta Modulator (SDM) is proposed. The output harmonic of DC—DC converter is well suppressed by the perfect noise-shaping property of the 3rd-order SDM. The transfer function of a SDM in a DC-DC converter system is thoroughly analyzed. Based on the analysis result, a complete loop design theory for the SDM based buck DC-DC converter is proposed, and the loop compensator of the proposed converter is designed under CCM and DCM, respectively.Based on above loss analysis and loop design, a low-power fast-transient-response buck DC-DC converter with perfect harmonic suppression under a wider load range is designed. An active-passive hybrid loop structure is chosen for the 3rd-order SDM to reduce the power dissipation. Dynamic width control of power MOSFET, Sigma-Delta pulse skip control, and dynamic dead-time control are proposed to improve the light load efficiecy of DC-DC. A non-linear fast transient controller is proposed to improve the transient reponse of the converter. Moreover, innovative structures are exploited in the on-chip current sensing circuit, the on-chip soft-start circuit, and the low-power voltage references, respectively. The input voltage of the DC-DC is 2.7～4.2 V, and the output voltage is 0.9 V. The off-chip components compose of a 2.2-μH inductor and a 4.7-μP capacitor. The input clock frequency of the SDM is 8 MHz. The circuit has been designed and fabricated using Chartered 0.35-μm CMOS process. Measurement results show that the conversion efficiency of the DC-DC is 78-90% under a load current range of 5～500 mA. The maximal output ripple voltage is 17 mV. With the load current skipping between 50 and 450 mA, the maximal output overshoot voltage is 82 mV. The harmonic tones of the output voltage are well surpressed under both CCM and DCM conditions.
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