Performance Optimization For Fault Tolerance On Switch Fabrics Of Scalable Routers

Scalable switch networks are key components of scalable routers whichplay very important role in the next generation Internet. Although faulttolerance is essential for scalable switch networks, it increases the redundancyand reduces system performance. Hence performance optimization for faulttolerance is a significant issue for the research and implementation of scalableswitch networks.In this thesis,we research on the key techniques of fault tolerant scalableswitch fabric,and our main goal is to optimize the performance of scalableswitch fabrics with failed components. This thesis is referred to three kinds ofoptimization techniques: topology robustness analysis, failure detection anddiagnose, resource allocation policy on switch nodes.The main contributions and conclusions are as follows:(1) A thorough survey is conducted on the research of performanceoptimization for fault tolerance on scalable switch network and its relatedresearch fields. It also introduces three critical aspects for performanceoptimization for fault tolerance on scalable switch networks.(2) A novel robustness measure named Failure Influence is proposed.Existing robustness measures are not suitable for scalable switch fabric underrandom fault model. It has been proved that Failure Influence is an effectivemeasure towards scalable switch fabric topology and it can distinguishrobustness difference among similar topologie.(3) Partial directional failure detector which based on partial directionalgossip algorithm is proposed. The consensus problem of partial directionalfailure detector is proved and an efficiency model is also introduced. Partialdirectional failure detector is outperforming existing hierarchal failuredetectors in both efficiency and message load.(4) Packet scheduler based resource allocation policy is proposed forswitch nodes, Extend hardware optimized bit reversal permutation is proposedand it has been proved to be an efficient resource allocation policy for scalableswitch fabrics. Hardware optimized bit reversal permutation can archive high scheduling performance with low implementation complexity.(5) A fault tolerant switch node prototype is introduced, which usespartial directional failure detector and hardware optimized bit reversalpermutation scheduler as its key parts. This prototype has larger capacities,lower implementation complexity and simpler expansion.