Analysis And Model Research Of40nm MOSFET Variation

The continuous scaling of CMOS devices to deep nano technology and inexorable reduction in supply voltage greatly challenge technology. The usage of new material and new techniques add or emphasizes physical effects such as polysilicon depletion, drain-induced threshold shift, proximity effect, reliability degradation, process induced variation growth, that are not important in the pasts. It continues to expand the requirements for MOSFET models.This paper focuses on the analysis and PSP modeling of layout dependent and process induced variation of40nm technology. In40nm MOSFET, layout variations of STI, well, gate, contact, active area bring physical and performance variation. Advanced SPICE models like BSIM and PSP have induced stress effect and the well proximity effect as intrinsic part, but without implementation of other layout proximity effect, which restricts the simulation accuracy. Meanwhile, process induced performance variation grows with the scaling and affects MOSFET in and out of die. Conventional corner model brings over-design problem. Statistical model based on Monte-Carlo get more attraction because it is much more physical-based and accurate.Modeling in this paper is based on PSP model, which is the Next-Generation standard MOSFET Model by Compact Model Council (CMC). Compared to the BSIM models that are threshold-voltage-based, PSP model is surface-potential based. It is more physics-based and has advantages in symmetry, validation both in subthreshold and strong inversion region, non-quasi-static effects.Through physics and data analysis, mobility and threshold voltage mechanism are induced. Model equations capture the correlation of variations and two PSP model parameters geometry independent flatband voltage vfb0and Zero-field mobility μ0are proposed. The model takes into account the impact of gate space and neighboring gates number; contact number, contact column number and distance of nearest contact and gate; lateral and vertical distance of nearest oxide diffusion; distance between nearest nwell and oxide diffusion. With the silicon verification of82test structure, threshold voltage change up to6-8mV and drain current change up to5%-7%and is modeled in the constructed model. Maximum transconductance is also monitored and shows good consistence.Device models are valuable when applied in device and circuit simulation. New LVS rules are revised to extract the value of layout variation instances. Successful extraction and simulation of netlist files validate the proposed model and LVS rules.Statistical variation nearly accounts for half of device variation in deep nano MOSFETs. Statistical model based on Monte-Carlo is established by modifying nine parameters are modified in PSP model:toxo (Gate oxide thickness), lap (Effective channel length reduction per sidedue to lateral diffusion of source/drain dopant ions), wot (Effective reduction of channel width perside due to lateral diffusion of channel-stop dopant ions), vfbo (geometry-independent flat-band voltage) and its geometry dependence parameter vfbw, vfbl and vfblw,μ0(Zero-field mobility) and thesatlw (area dependence of velocity saturation parameter). The simulation result verifies the accuracy of the model, the error of standard deviation is controlled within5%and the error of mean value within2%, which is up to the industry standard. This proposed model could optimize the circuit design and ensure the tape out success.