| Turbo code is a powerful error correcting technique that has been used in many fields such as deep space communications, wireless mobile information transmission, digital subscriber loop, and large capacity magnetic storage. Factor graph is a bipartite graph that expresses how a "global" function of many variables factors into a product of "local" functions. A wide variety of problems developed in artificial intelligence, digital communications, and signal processing can be described by factor graphs. By a general process named sum-product algorithm that distributed propagate the probability information in the corresponding factor graph, many problems can be solved, and the iterative decoding algorithm of turbo codes can also be viewed as a special instance of sum-product algorithm. The sum-product algorithm (probability propagation) can be mapped directly into analog transistor circuits with its intrinsic linear property. These circuits enable the construction of analog VLSI decoders, the analog decoder can work at higher data rates than equivalent digital decoders, they can have a smaller size and lower power consumption.The paper focused on the study of graphical model of turbo codes and its corresponding decoding algorithm. And then after that, the author studies the design and implementation of analog VLSI turbo code decoder. The research process and some research conclusions are as fellows:(1) The trellis termination problem of turbo codes are researched, the effect of some different termination methods on the performance of turbo codes are analyzed and tested by simulations, it shows that using tail-biting RSC code as component code, turbo code may has better performance without the decrease of code rate while the complexity of encoding and decoding increases little, this turbo code has the advantage that all the information data are protected equally.(2) Turbo codes and LDPC codes both have their advantages and can achieve the Shannon limited performance. The constituent RSC codes in turbo codes are more structural and this lends the encoding problem easier with shift-register circuit. While the encoding of LDPC codes is performed via matrix multiplication, and this is more complex than it appears for capacity-approaching LDPC codes. On the other hand, the soft-input soft-output BCJR algorithm, or the sub-optimal version of it, used for turbo-decoding is rather complex while sum-product algorithm used for LDPC decoding lends itself to parallel implementation and is computationally simpler. Combining the turbo codes encoding and LDPC decoding, a new scheme based on factorgraphs and sum-product algorithm is developed, it can reduce the decoding complexity of turbo codes greatly.(3) The graph models of turbo code are studied detailed; the parity-check matrix of turbo code and its property are also analyzed. Observe that the parity-check matrix of turbo codes are also sparse, it can be say that turbo codes are special kinds of LDPC codes essentially. Using the results in LDPC codes, convolutional codes that have the property of self-orthogonal are better to be chosen as component code. (4) The factor graph based sum-product algorithm and its implementation in analog VLSI are studied. The basic building modules of that analog-decoding network are analyzed and developed, and the general method on the design of analog VLSI decoder is also given. It shows that in the sum-product decoding algorithm based on binary factor (Tanner graph), there are types of basic operation named arithmetic summation and "cycle plus" of two likelihood values (L) that can all be mapped into a transistor network realization based on the Gilbert four-quadrant multiplier. In this case, voltages correspond to the L values. For the sum-product decoding algorithm based on trellis, currents are often correspond to the probability messages and the whole decoding networks can be achieved by build the general trellis computation elements. All these enable the modularization of analog VLSI decoder.(5) Using voltage or c...
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