| Test challenges brought by advancement of IC processes and enlargement of chip scales require thatBuilt-in Self-test (BIST) should be included in more and more chips. However, power dissipation is con-siderably higher in test mode than in functional mode because of two reasons. Firstly, correlation betweenconsecutive test patterns is very low. Secondly, in order to minimize test application time, concurrent teststrategy is required. Therefore, many blocks will be active at the same time leading to a con?ict with thepower management policy. This extra power consumption due to test application may be responsible forcircuit reliability reduction, yield decrease, higher package cost and so on. This paper focuses on low powerBIST design methodologies, including power-constraint BIST design in high level testability synthesis andlow power BIST design in logic level.The first part of this dissertation addresses power-constraint BIST design in high level testability syn-thesis (HLTS). The objective of HLTS is to accomplish data path structure design and BIST circuit designsimultaneously during the behavioral description of a design is transformed into structural implementation.In this paper test power consideration is introduced in HLTS and normal registers are used in BIST design.In order to achieve those goals, the random response model of functional modules, which is used to quantifythe controllability and observability of behavioral variables, is established and the relationship between faultcoverage and testability metrics is explored by means of fault simulation. Based on this, test resources whichcan be used in testability synthesis is distinguished. In power-constraint HLTS, the relationship between testresources and modules under test is represented as binary variables and test power is modeled from the pointof view of test path. The ILP based method searches optimal solution in pseudo-random testability underpower constraints. Experiment results show that power constraint is not violated in any test session and areaoverhead is minimum compared with other HLTS methods.The second part of this dissertation focuses on low power BIST design in logic level, by means ofpower-oriented test structure and test pattern generation optimization. The proposed partial-scan based lowpower BIST method adopts"Test-per-Scan"test structure, combines partial scan and"pipeline"test operationfashion to reduce test power on the condition that fault coverage is guaranteed. This method is very suitablefor sequential logic BIST design. In power-oriented test pattern generation method, first of all, effective testvectors are distinguished from test patterns by Simulated Annealing algorithm, and then skipping logic isdesigned to skip ineffective vectors during test pattern generation. This method can be used to reduce powerdissipation of combinational logic. Because scan test is commonly used in industry, low power scan designmethod is put forward and can used to substitute for partial-scan based low power BIST method.Low power BIST methods at various stages of the VLSI design ?ow are offered in this paper. Duringhigh level synthesis, low test power, low area overhead RTL structure can be generated based on powerconstraints and random response model of functional modules. During logic level synthesis, test power canbe minimized at little cost of fault coverage and area overhead. At last, a summary is given and some pursuedproblems about low power testing are pointed out. |
