Low Power Design For Key Circuits Of Baseband Processor In Wireless Sensor Network Nodes

Since energy efficiency is a key concern in the research work of WSN, it is important to design a low power node. So the dissertation puts the emphasis on the low power design of the Viterbi decoder (VD) and the BPSK direct sequence spread spectrum (DSSS) which both belong to the baseband processing.In the dissertation, first, we presented a low power implementation of a VD (rate 1/3 and constraint length 9), which was achieved by applying some algorithmic modification on the conventional structure, and then employing several low power design techniques; according to the symmetric characteristics of the generator polynomials, the complexity of branch metric unit (BMU) could be simplified about 80%; based on the pre-computation technique, the transition activity of the components in add-compare- select (ACS) could be reduced more than 12.5%; during the in-place path metric update, a state mapping address (SMA) was proposed to make the newly computed path metric write into the correct physical address (PA), and comparing with the ping-pong structure, approximately 46% power dissipation of SMA update could be reduced by the MSB flag; also with the MSB flag and the assigned pointer, the update operations of survivor memory unit (SMU) could be minimized; in addition, with a termination signal to prevent the useless activities in SMU, the power dissipation could be decreased around 30%.As current spread spectrum chips were not completely fit for the characteristics of WSN, the former series node devices had to realize the DS/BPSK technique with DSP or FPGA, which led to high power consumption for the inefficiencies; since SoC was the trend of node progressing, therefore, we hoped to develop a series of chips that were special for sensor node, and the first DS/BPSK chip interiorly was one of them, which was fabricated in TSMC 0.25μm CMOS process technology with the area 2×2 mm~2; and the active current in chip was about 6mA at 3.3V and 58.5MHz which was obviously less than the one with DSP or FPGA. Due to the high glitch power dissipation in chip test, we analyzed the reason for glitch generation and propagation, and studied the techniques that attempt to reduce glitches in control or data signals, as well as methods that could decrease register power consumption by gated clock; by comparing various gate triggerings with MOS transistor, we modified the design of some modules in DS/BPSK chip, which belonged to the non-critical path and appeared glitches frequently.Finally, the motivation of the dissertation originated from "CDMA wireless sensor network" which belonged to Intellectual Innovation Project of Chinese Academy of Sciences; some work of the dissertation could be help to accelerate the development of WSN node towards miniaturization and low power way.