Research On Technologies And Implementation Of Low-Density Parity-Check Codes

Low-Density Parity-Check(LDPC)Codes is one of the most popular topics in the research area of digital communications in recent years.LDPC codes were proposed by Gallager in 1960's,but people did not pay much attention to it at that time,just because of the poor technology of computers and hardware.Since 1990's,with the great improvements of computers and hardware,LDPC codes have gradually regained the interests of researchers.People found that LDPC codes have many encouraging characteristics,such as they can provide near-capacity performance with very low error-floor,they have very simple decoder structures,which is suitable for fully parallel implementation,and so on.But as a kind of new error-correcting codes,there are still many problems should be addressed,before LDPC codes can be utilized in practical systems.The author has been working on the construction,encoding,decoding,and FPGA implementation of LDPC codes,with the principle of reducing the implementation complexity of LDPC codes while maintaining their good performance.Some achievements about LDPC codes are proposed in this dissertation,including a complete solution for implementation of LDPC codes.Some primary achievements of this dissertation are listed below.Decoding algorithm is a very important part in the research area of LDPC codes. The author studies the features of BP algorithm and MS algorithm,then propose a new soft-decision decoding algorithm,named as "MZS algorithm".The performance of MZS algorithm is almost as good as that of the BP algorithm,but with much lower complexity.The girth of parity check matrix is very crucial for the performance of LDPC codes.Generally,only LDPC codes with girth larger than 4 can provide good performance.Usually it is not easy to construct LDPC codes with girth larger than 8, with the restriction that the column weight is not less than 3.The author constructs a kind of QC-LDPC codes,named as "3D-LDPC codes" with girth larger than 8 and column weight larger than 3.3D-LDPC codes can provide the same good performance just as the irregular LDPC codes do,what is more,as a kind of QC-LDPC codes,3D-LDPC codes also have some advantages in implementation. QC-LDPC codes are very popular in recent years,because their special structures can help a lot in reducing the implementation complexity.The author proposes a kind of special QC-LDPC codes,named as "QSBC-LDPC codes".The encoding process of QSBC-LDPC codes can be finished in recursive way with the parity-check matrix,so the complexity of encoders is very low,and the performance of QSBC-LDPC codes is also very good,The author believes that QSBC-LDPC codes is very good candidate for practical utilization.The author also proposes two recursive encoding structures for the QSBC-LDPC codes with FPGA.These two encoding structures are essentially the same,but they are optimized for different goals.One encoding structure is optimized for high encoding throughput and the other is for low resource consumption.Both the two encoding structures can provide encoding throughput over Gbps.An improved MSA decoder structure for FPGA implementation is also proposed in this dissertation.The author studies a general memory efficient decoder structure for common QC-LDPC codes,and makes some modifications according to the special structure of the parity-check matrix of QC-LDPC codes.The improved MSA decoder structure is only for QSBC-LDPC codes,and it can provide high decoding throughput with less resource consumption than the general MSA decoder for common QC-LDPC codes.S-LDPC code is a kind of special LDPC codes,with very low encoding complexity and poor performance.According to this,the author combines the parallel structure with 3D-LDPC Codes,and proposes the PCS-LDPC codes.This design can significantly decrease the implementation complexity,while only tiny performance degradation is found according to the simulations.PCS-LDPC Code is very suitable for applications in practical systemsThe author also studies the effect of unequal power allocation for S-LDPC codes, and gives some theory analysis with Semi-Gaussian algorithm.The author finds that, with unequal power allocation method,an optimal power allocation parameter can be found,and the performance of S-LDPC codes can be effectively enhanced with almost no complexity increment to the whole system.All the error-correcting codes are designed for practical applications,so it will be meaningless and regretful if a kind of error-correcting codes with good performance can not be realized.The research results in this dissertation make it easier and more possible to realize and utilize LDPC codes in practical systems,some of the achievements in this dissertation are of international level.The author believes that this dissertation can be good reference for further research in implementation of LDPC codes.