| The digital television (DTV) is replacing the analog television to become a new information industry gradually, and it will eventually raise a new high economic tide. The IC chips for DTV is critical. As the development of VLSI technology and EDA tools, the incessant increasing requirement of DTV application, the scale of chip and functions are also increasing accordingly, the integration and complexity are more and more higher. Single-chip and integration have already been the trend of DTV chip development currently. This paper mainly focuses on the research and design about architecture and algorithm of cable-DTV SoC chip, analyses and discusses the channel demodulate/decode algorithm, the hardware/software co-design of each function part, system tasks schedule and On-Chip Bus (OCB) design. Finally, provides the solution and research result. The structure of this paper is arranged as follows.In the second chapter, a hardware/software co-design tactic which adapts to cable DTV SoC chip has been proposed, based on the method, process and technic of hardware/software co-design. In term of the idea about hierarchical design for SoC, the system architecture partition at the most coarse granularity has been taken. The partition weakens the coupling between channel modules and source modules, is convenient for design and system extension or update in the future.The third chapter focuses on the research about channel demodulate/decode part. Under DVB-C standard, analyses and discusses some module which affect the performance of receiver critically, such as carrier-recover, timing-recover and equalizer, provides the implement scheme. According to the tactic of SoC design, the channel sub-system has been partitioned and structured by the algorithm flow. With hardware/software co-design idea, analyses and researches the mode of each function module implementation. According as the function characteristic of manage sub-system, proposes hardware/software co-design method based on ASIP, provides the design flow of ASIP, completes the instructions set, hardware architecture design and code assembler design, also provides the software execute flow.The fourth chapter researches the source part in the chip. According to the function, the source part can be partitioned four sub-parts, which are system-level parsing, audio decoding, HDTV video decoding and multimedia application. At various granularity level, analyses each task by its implement aim and operation complexity. Also considering the real-time, flexibility and integration, decides each task and sub-task implement mode, provides the high efficiency solution, meets the real-time requirement and decreases the cost. Thereinto, in multimedia process section, usingMPEG-4 video decoding as illustration, analyses the operation cost of software mode, provides the software implant flow and optimizing technique. According as the characteristic of tasks themselves and MCUs, proposes "RISC+DSF" double-core architecture, in order to meet real-time and flexibility requirement.The fifth chapter analyses the main task in cable DTV SoC chip. Through task mapping, the task has been divided into master processor task and vide decoding task. According to the characteristic of task and system requirement, makes the proper schedule scheme and granularity, optimizes the structure and process flow. For the OCB, through analyzing the bus bandwidth requirement, proposes the multi-buses architecture. Especially for the system bus whose bandwidth requirement is most critical, adopts double-bus architecture. Each sub-bus of system bus has different bitwise. Proposes a static time division multiplexed with dynamic fixed priority arbitration scheme. Through analyzing the characteristic of media process task, establishes centralized arbitration architecture. Provides a schedule structure based on kernel arbitrator to realizing the data transaction between the system bus and local bus.The last chapter is the summary of this paper and the perspective of the future work.
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