Codec Implementation And Application Of A Family Of Protograph-Based LDPC Codes

Achieving reliable communication approaching channel capacity is the ultimate object of digital communication technique. One of the way realizing this goal is using channel coding. The invention and development of low-density parity-check codes (LDPC) narrow the gap between real system performance and channel capacity. Combining the existing theoretic and practical fruits, researchers focus on the designing of powerful LDPC codes with low coding and decoding complexity. In this thesis, studies are devoted to LDPC codes design and analysis, LDPC codec algorithms and implementations, as well as LDPC coding applications in multilevel coding schemes.Firstly, inspired by Repeat-Accumulate (RA) codes, an innovative channel coding scheme called Accumulate-Repeat- Accumulate-Partial-Accumulate(ARAPA) codes is proposed, and theoretical analysis is also taken. At the same time, a method of expanding protographs is contrived. This method includes two steps . The aim of the first step are eliminating multi-edges and increasing the girth length as large as possible. On the constraint of girth length, the second step focus on obtaining quasi-cyclic LDPC codes. The codes which conceived from above methods not only implement easily but also suit for high speed decoding. The results of theoretical analysis and computer simulation show that the iterative decoding threshold of ARAPA protograph LDPC codes are very low, and the minimum distance of these codes grow linearly with code block size. In addition, the performance of ARAPA protograph LDPC codes is not only better than R.U LDPC codes but also AR4JA protograph LDPC codes which are commended to CCSDS by JPL when the rate bigger than 0.5. Moreover, the decoding complexity of ARAPA codes is lower than AR4JA codes.Secondly, the encoding algorithm and encoder implementation are studied. Using the quasi-cyclic property of the parity check matrix, the method for computing quasi-cyclic generator matrix is derived from isomorphism between matrix ring and polynomial ring and extended Euclid's algorithm. Next, according to the characteristics of quasi-cyclic matrix, a new encoding circuit using feedback shift registers is proposed and implemented by FPGA.Thirdly, the decoding algorithm and decoder implementation are studied. Based on the study of message schedules for iterative decoding, pointing out that ARAPA protograph LDPC codes are suitable for Parallel Turbo-decoding message-passing (TDMP) scheduling. After analyzing message magnitudes which are estimated by Min-Sum and A-min algorithms, a new hybrid algorithm compromising performance and complexity is proposed. Compared with BP, this algorithm is 0.1 dB loss. Since coding gain is very important to deep space communication, a decoder is implemented using TDMP scheduling and A-min algorithm based on the characters of ARAPA protograph LDPC codes.Finally, a multilevel coding (MLC) scheme with ARAPA protograph LDPC codes as component codes is designed. This scheme takes both bandwidth and power efficiency into account. The simulation result showed that on the condition of 8PSK modulation, 2 bits/symbol, error bit rate at 10-5, adopting ARAPA protograph LDPC codes with length of 4096 as component codes, the performance gap between this system and Shannon limit is only 1.48dB.