Research On Impulse UWB Synchronization Techniques

The utilization of smart synchronization technology is a very sensitive and important issue in Impulse Radio Ultra-Wideband (IR-UWB) systems for many reasons. Firstly, small resolution search is caused by broadband, resulting in the inclusion of larger search area during acquisition process. Also, the use of extremely narrow pulse with low duty cycle have inherent multi-path effect, i.e. more than one multi-path will satisfy the synchronization threshold, yielding misjudgment. Secondly, frequency offset between receiver and transmitter is omnipresent, unavoidable, and introduces significant BER in IR-UWB system. Thirdly, the existing network clock synchronization algorithms can not meet the requirements of synchronization accuracy and overload from the distributed network of IR-UWB. In order to solve synchronization problems in IR-UWB system under intensive multi-path conditions, synchronization in IR-UWB system is studied in depth, including acquisition at the physical layer, frequency offset problem, time synchronization at the network layer and hardware realization of IR-UWB platform.A mathematical model of IR-UWB system is established, and different receiving modes for IR-UWB system are studied. Receiving modes based on transmitted reference, energy detection and correlation detection are theoretically analyzed and compared. Two important synchronization parameters, i.e., Mean Acquisition Time (MAT) and False Alarm Rate (FAR) are analyzed. In latter simulations, MAT and FAR for different receiving modes are compared in four IEEE _UWB channels.Firstly, a rapid acquisition algorithm adopting variable step searching strategy is proposed. Classic rapid acquisition algorithms are targeted at improving MAT, without acquisition accuracy considerations. To address this issue, a novel rapid acquisition algorithm, called Variable Step Algorithm (VSA), aimed at improving acquisition accuracy and MAT at the same time, is proposed. Theoretical deduction of MAT and FAR formulae for VSA is performed which provide analytical grounds for VSA synchronization performance comparisons. Empirical algorithms and VSA are compared with respect to synchronization performance. Simulations reveal that VSA outperforms classic algorithms with a shorter acquisition time and more accurate precision.Secondly, an anti-jitter timing method incorporating Fractional Fourier domain is proposed. Given the important role of frequency offset in IR-UWB system and its effect on frequency offset estimation in time domain, a new frequency offset estimation system adopting Fractional Fourier domain is proposed. The system kernel lies in frequency offset estimation algorithm, which includes both time domain and Fractional domain. The estimation algorithm adds chirp signals to UWB pulses and chooses the appropriate Fractional domain in order to achieve frequency offset estimation and acquisition forecast. A scheme for UWB acquisition forecasting in this system is also proposed and tested. In thorough simulative analysis, forecasted acquisition adopting Fractional Fourier domain is compared with regular acquisition in time domain, which confirmed that MAT and FAR can be improved by using proposed scheme.Then, a novel clock synchronization algorithm suitable for IR-UWB distributed network is proposed. Through the analysis of ultra-wideband network physical layer characteristics, the existing network clock synchronization algorithm might not meet network overhead and accuracy requirements. Thus, a novel time synchronization algorithm providing clock frequency offset, considering several delay measurement results, and based on pair-wised model is proposed, referred to as Dual Line Estimation Algorithm (DLEA). The new algorithm is implemented in two steps, i.e., data collection and frequency offset estimation. Then, the local clock is to be adjusted according to the estimations. Simulations reveal that DLEA synchronization accuracy is superior to the traditional clock synchronization algorithm, and has the advantage of lower network cost.Finally, we have verified the synchronization algorithm on the FPGA-based UWB hardware platform. Core design principles for UWB hardware platform are introduced; including the design of its main transmitter, receiver and synchronization module with due focus on FPGA design and simulation setup. Proposed VSA is also verified in FPGA, and the design includes acquisition and verification modules. After implementing the hardware debugger, error frame rate for UWB platform reaches the order of magnitude 10-6, with a good synchronization performance.