Research On Low Power Design Methods Of Bus And OCN Interconnection

The rapid growth of power dissipation has become a significant problem to the development of SoC. The globally asynchronous OCN (on Chip Network) architecture overcame the intrinsic problems of bus architecture such as the expansion of bandwidth and a lower communication efficiency, and decreased the rapid growth of power dissipation induced by globally synchronization. Bus architecture is still used for local communication because of its simple structure and easier implementation. An effective combination of OCN and bus architecture is the trend for future SoC.Long interconnects and their drivers are key determinants of system performance and important sources of dynamic power dissipation. Bus in SoC and interconnects of OCN both have the characteristics of long length and high operating frequency. Therefore, this paper focuses on low-power design methods of long interconnects with bus and OCN as research objects. The researches and results of this paper are as follows.1. Research on the analytical model of bus dynamic power dissipation and low-power routingBased on the simplified model of bus dynamic power dissipation in deep sub-micron, according to the transition of adjacent lines, we build the characterization of coupling dynamic dissipation of the adjacent lines so as to calculate the bus power dissipation during successive periods and obtain the computing method of the coupling power factor and activity. According to program address data, we calculate the coupling power factor and activity of every bit line and proposed low-power routing scheme. First route the two lines with high activity on the two sides of the routing channel. Then search out the line which has the smallest adjacent coupling power factor with the routed lines and route it on the inner sides. Final repeat and determine the order of all bus lines. By combining with the traditional low-power routing methods, we obtain several low-power routing methods, in which the scheme that increases distance between the two side lines and the inner lines reduces the dynamic power dissipation of the program address data by 38% with an increase of 3% in routing area.2. Design and verification of the 16-bit fixed-point DSPWe design the 16-bit fixed-point DSP compatible with 320C50 instructions using Verilog HDL. We verify the correctness of the design by instruction verification, functional verification and FPGA verification, and obtain data stream of the DSP bus, which provide the foundation for the research on the low-power DSP bus encoding technology.3. Research low-power bus encoding methodsFor program address bus of the 16-bit fixed-point DSP, we propose the adaptive low-power bus encoding: for the jump of cycling program, it keeps the original transmitted address; for the jump of non-cycling program, it transfers the real address and updates the initial address. The method reduces the power dissipation of program address bus by 76.4%. For the output bus interface of the color CMOS image sensors, according to the characteristic of high relativity and low activity of the first six bits of the homochromatic pixel signals, an encoding algorithm is given. According to the comparative results of the first six bits of present and previous homochromatic pixels, it decides whether the corresponding first six bits remain, thereby reducing the activity of the interface signals and saving 24.2% dynamic power dissipation of the interface. For the growing crosstalk between adjacent interconnects, we propose an encoding approach to transmit the worst case crosstalk data with two cycles to suppress the worst case crosstalk: for the worst case crosstalk data, in the first cycle retain the even bits and update the odd bits, while in the second cycle retain the odd bits and update the even bits. The method eliminates the worst case crosstalk, reduces the jitter range of the propagation delay, and improves system operating frequency (20%). Combining with Codebook encoding further improves system operating frequency and reduces energy consumption.4. Architecture implementation and low-power interconnects design of 3×3 OCNBased on 2-dimension mesh topology, XY router algorithm and wormhole routing, we propose an NI structure with packet making and disassembling executed independently. We implement the router by using dual-ported memory to store/transmit data in order to reduce delay and configuring memory depth properly in order to increase throughput rate. Based on the discussion above, we design and verify a 3×3 OCN communication architecture, which provides the foundation for the optimization design of OCN interconnects. The crosstalk of adjacent long interconnects between OCN routers induces large signal jitter. Based on the analytical model of interconnect payload, we propose an approach that according to the payload obtained by comparing adjacent signals, the signal drive strength is adjusted to stabilize the propagation delay and suppress signal jitter. Compared with the buffer-drive mode, the proposed drive mode has a 29.6% decrease in signal jitter and an effective increase in the highest clock frequency with the same ratio between width to length at the driver stage when the length, width and spacing of interconnects are 2mm, 0.4μm and 0.4μm respectively.The paper discusses several mechanisms to reduce power dissipation of long interconnects such as low-power routing, low-power bus encoding and low-swing circuit and so on and proposed several new low-power design methods. By taking into account the crosstalk and power dissipation of long interconnects, a crosstalk avoidance low-power encoding scheme and an adaptive variable drive strength scheme are proposed to improve operating frequency by avoiding the worst case crosstalk and reduce power dissipation under required data bandwidth. The platform for power dissipation analysis of SoC long interconnects and low-power design methods this paper proposed provide an significant technology foundation for novel SoC low-power design.