Research On Key Technologies Of LDPC Codes In High Data Rate Transmission

Low-Density Parity-Check (LDPC) code, which was rediscovered in recent years, is a milestone in channel coding domain. Its outstanding error-correction performance and natural parallel decoding algorithm result in its application in several international communication standards. This dissertation discusses the LDPC code's application in high data rate transmission, and stresses several tasks below.1. Two novel methods for constructing structured binary LDPC codes satisfying the row-column constraint are proposed. One is based on cyclic groups, and the other is based on finite fields. The structured LDPC codes constructed by both of these methods have girths at least 6. Experimental results show that the constructed LDPC codes decoded with BP algorithm over the AWGN channel can achieve good bit error rate (BER) performance.2. An efficient method for designing highly-parallel decoder architecture of quasi-cyclic (QC) LDPC codes is presented. The key point for highly-parallel decoder architecture of a QC-LDPC code is how to deal with a large amount of memory reading and writing in an orderly manner so as to avoid/reduce the memory access collision. Code transformation is a way to solve the issue. QC-LDPC codes can be transformed into (approximate) block quasi-cyclic (BQC) LDPC codes. (Approximate) BQC-LDPC codes have high speed decoding advantage over other types of LDPC codes for SBP or LBP algorithm. Both a highly-parallel LBP decoder and a highly-parallel SBP decoder for (approximate) BQC-LDPC codes are proposed. Moreover, their architectures are discussed in detail, and compared with the existing decoders.3. The issue on efficient encoding of BQC-LDPC codes is addressed. A method is presented to find the block quasi-cyclic generator matrices of BQC-LDPC codes from their parity-check matrices, given in block quasi-cyclic form. Based on the block quasi-cyclic generator matrix of a BQC-LDPC code, two types of encoding circuits using simple shift registers are designed. One is designed for efficient encoding of a BQC-LDPC code, its encoding complexity is linearly proportional to the number of parity bits of the code. The other is designed for high-speed parallel encoding. These encoding circuits combined with code transformation can also be applied to encoding of some QC-LDPC codes.4. A new construction method for QC-LDPC convolutional codes is proposed based on QC-LDPC block codes. Similar to QC-LDPC block codes, these LDPC convolutional codes not only simplify decoder design but also require less memory storage. Simulation results show that the constructed LDPC convolutional codes decoded with pipelined BP algorithm over the AWGN channel can achieve good BER performance. A pipelined LBP algorithm for decoding LDPC convolutional codes is proposed, and a type of decoder architecture for QC-LDPC convolutional codes is designed based on the pipelined LBP algorithm. The pipelined LBP decoder architecture has some advantages in speed and complexity over the pipelined SBP decoder architecture.5. Both an encoder and a decoder with throughput of 800 Mbps are implemented in Field Programmable Gate Array (FPGA) for (8176,7154) Finite-Geometry QC-LDPC code.