Methodologies For SOC Hw/sw Verification And FPGA Testing

The development of an SOC chip consists of several stages, including design, verification, manufacturing and so on. And among them, verification costs 70%-80% of the whole SOC developing time and cost. Therefore, research on SOC verification becomes an essential part in today's IC industry.In this dissertation, hardware/software cosimulation and its application on FPGA chip testing have been done. There are mainly four major works.The First, in order to implement both architecture and transaction level verification on the same platform, a flexible SOC cosimulation architecture consists of four layers is proposed, namely, application layer, transaction layer, transport layer and communication layer. Different requirements for SOC verification with different communication channels (PCI, USB, PCI-E, Ethernet, etc), different simulation models (transaction model, architecture model, etc) and various design languages (ASM, C/C++, Verilog/VHDL, etc) can be met by our platform.The Second, an innovative SOC hardware/software communication protocol is proposed, which defines the synchronization mechanism between EDA software on host PC and Design Under Test (DUT) on hardware accelerator. Based on this protocol, FPGA testing platform is designed in this dissertation. Research on stream-mode hardware/software communication is also performed, which could increase the cosimulation speed. Based on our platform, some SOC cases, including FIR Filter, H.264 Decoder, and Frequency Discriminator have been verified.The Third, the idea of FPGA chip testing on the proposed cosimulation platform is proposed for the first time. Compared with existing Automatic Test Equipment (ATE), which is widely adopted in the industry, the proposed method integrates the flexibility of software and high speed feature of hardware, providing huge storage on host PC and numerous available I/O pins for the target chip. Fault unit in FPGA can be detected automatically with such method, which increases FPGA test speed and reliability and reduces test cost. With hardware/software cosimulation technology, test vectors from design phase can be directly applied to chip testing, which integrates the chip design and verification, and reduces the required time to market.The Fourth, FPGA full coverage testing algorithm from the aspect of graph theory, logic resource cascading, test wire driving capacity enhancement and test resource monitoring has been investigated. The proposed method fills the gap in IOB and WEB full coverage test first time internationally. The test algorithm allows CLB test with 5 times configuration (6 times are needed normally) and 88.3% coverage IR test with no more than 6 times configuration (no early report on such result was published). The proposed algorithm, combined with SOC hardware/software cosimulation methodology, provides an innovative full coverage FPGA test method with our own intellectual property rights. With the proposed method, full coverage FPGA test on XC4000 series FPGA from Xilinx is carried out.Finally, future work of SOC verification is discussed. Research on several aspects, such as DUT full observability, ESL design and verification method and digital-analog mixed simulation methodology can be carried on.