The Research And Implementation Of The Readout System For A New Plastic Scintillator Array Detector

The research of dark matter detection in the field of particle physics and astrophysics is a very popular subject in recent years. So the project of space exploration for dark matter detection which supported by space technology pilot program of Chinese Academy of Sciences will be planned to build and launch a scientific mission satellite to find the evidences of dark matter particle for future research.As one of the important subsystem in the satellite,the new type of plastic scintillator array detector which is developed by the institute of modern physics,Chinese academy of sciences is used to distinguish photons and electrons in a high-energy particle beam from near-earth space and complete particle identification with the number of proton Z = 1 ~ 20. In order to achieve the mission requirements, it is carried out the research on the key technical of hardware structure and FPGA control logic design of the front end readout system for this array detector. In view of the low power consumption, high reliability and many other strict requirements, solutions and countermeasures are discussed. Furthermore, it is also introduced in detail about the ground testing system in this paper.The readout system for new array detector mainly includes 4 front-end readout electronics circuit(FEE). There are 360 input channels in its minimum application system and 512 input channels at most extended. Each FEE’s constitution is based on the advanced charge measurement circuit and the high performance FPGA. The charge measurement circuit is adopted the special-purpose integrated circuit(ASIC) chip VA32HDR14.2 and 16 bits digital chip AD976 A. They carry out the tasks of sampling, processing, holding, digitizing and buffering the detector’s output signal under the control of FPGA. Moreover, FPGA chip which is adopted from the space level production of Actel firm in American, completes the tasks of control to the charge measurement circuit and monitoring for other functional circuits.The front-end electronic system has the characteristic of low power consumption, modularization, easy to extension, high versatility, etc. The FEE circuit has a good portability and scalability and it is easy to copy to build large multi-channel front-end readout system. It also has the functions such as self-protection ability, high reliability, which not only can be used for the spatial particle detector signal processing, but also is used for particle physics experiment ground detector signal processing.A number of confirmation tests for FEE readout system in this paper mainly include: the FPGA logic simulation, FEE without detector circuit testing and FEE with detector circuit testing under laboratory environment. The former can test the readout electronics system function and its linearity, noise, stability, crosstalk, and other indicators; The latter by detector system self-calibration and cosmic ray test, can evaluate the overall performance of the readout system and decide whether it achieves the desired science objective. The experimental results indicate that the current readout system solutions in general can meet the demand of the array detector system of readout.