Research On Steadv-state Analysis And Capacitor Voltage Balancing Method For Modular Multilevel Converters

Recently, voltage source converter based high voltage direct current (VSC-HVDC) transmission is widely used all around the world. Compared with the alternating current (AC) transmission and conventional line commutated converter based high voltage direct current (LCC-HVDC) transmission, VSC-HVDC is a potential candidate in the area of renewable energy power generation, islanding power supply and grid interconnection since it can control the active and reactive power independently, reverse the power flow easily, self-commutate without grid support and black start fast. As a state-of-the-art voltage source converter, modular multilevel converter (MMC) combines the advantages of clamped multilevel converters and cascaded H-bridge multilevel converters. It is convenient to expand the voltage levels to an arbitrary number by stacking the identical sub-modules, which results in high voltage power conversion and low voltage distortion. Meanwhile, it is easy to realize mass manufacture in the industry application due to its highly modular structure. As a result, MMC becomes a major topic in the academy and industry. In this paper, a four order large signal model is built and a solution for the steady-state arm currents and capacitor voltages is discussed. Then a fundamental frequency sorting algorithm based capacitor voltage balancing method is proposed for nearest level modulation (NLM) and carrier phase-shift pulse width modulation (CPS-PWM) with low carrier frequency. Moreover, a capacitor voltage balancing method with segmental logical processing is proposed for CPS-PWM with high carrier frequency to accelerate the convergence rate.Firstly, the equivalent circuit model are obtained from topology derivation and a 2N+2 order universal model which adopts the arm inductor currents and capacitor voltages as the state variables is built. Considering the balancing performance of the capacitor voltages in the steady state, the universal model can be simplified to a four order large signal model with the state variables of the summation of all the capacitor voltages, the difference between the total voltages of the upper arm and lower arm, the circulating current and the output current. Referring to calculating the quiescent point of the DC-DC circuit from the large signal model, the accurate steady-state expressions of the arm currents and the average capacitor voltages can be obtained from the four order large signal model. This is quite beneficial for the selection of the arm inductors and sub-module capacitors.Secondly, the charging characteristics of the driving signals generated from NLM and CPS-PWM with low carrier frequency are analyzed in detail. Then a fundamental frequency sorting algorithm based capacitor voltage balancing method is proposed. It evaluates the charging capabilities of the driving signals via the corresponding voltage increments in the last fundamental period. A dual sorting mechanism, which sorts the voltage increments and present voltages simultaneously, is implemented at every fundamental period to re-build the corresponding relationship between the driving signals and the sub-modules. The driving signal with larger voltage increment is assigned to the sub-module with lower capacitor voltage and the driving signal with smaller voltage increment is allocated to the sub-module with higher capacitor voltage. With this method, the sorting frequency can be effectively reduced and many calculation resources can be saved. The swiching frequencies of the sub-modules are equal to each other and no extra switching commutations are generated. Meanwhile, it does not need to measure the arm currents. Furthermore, an improved strategy is put forwad to simplify the dual sorting mechanism according to the approximately symmetrical characteristic of the curve between voltage increment and driving signal number. Thus, the sorting of voltage increments can be eliminated.Thirdly, the convergence rate of the previous balancing method for CPS-PWM with high carrier frequency is slow under disturbance or initial unbalance case. It can be verified that the charging capabilities of two driving signals for CPS-PWM with high carrier frequency can be largely changed via logical AND and logical OR. The charging capabilities of the new driving signals which are acquired by logical processing mainly depend on the corresponding phase-shift angle of the two original driving signals. Based on it, a capacitor voltage balancing method with segmental logical processing is proposed to accelerate the convergence rate. At first, classify the submodules into N/2 groups with the principles that the submodules with the highest and lowest capacitor voltage are in one group, the sub-modules with the second highest and second lowest capacitor voltage are in one group and so on. If the voltage difference in one group is smaller than the set value of convergence, assign the driving signals to the sub-modules directly. If the voltage difference in one group is larger than the set convergence value, select two driving signals with suitable phase-shift angles for the corresponding carriers at first and then process them with logical AND and logical OR before they are assigned to the sub-modules. In this way, all the capacitor voltages can be balanced well. The sorting frequency is decreased to fundamental frequency and the switching frequencies of the sub-modules are equal to the carrier frequency. Moreover, it does not need to measure the arm currents.Finally, a three-phase experimental prototype with 48 sub-modules is assembled to validate the theoretical steady-state analysis and the capacitor voltage balancing methods. A three-level dendritic control architecture is adopted, which is made up of central controller, phase controllers and sub-module controllers. It is convenient to expand the sub-module scales for this control system. The information which is modulated into the square waves with different frequencies is transmitted from the phase controller to the sub-module controllers through a optical fiber, where the optical fiber multiplex technique is adopted. The other information exchanges between different controllers are all in the serial communication mode.