Reas Earch On Key Technologies Of Single-Stage APFC Voltage-Fed Full-Bridge Battery Charger

Voltage-fed single-stage APFC full-bridge converter becomes an attractive topic in high quality large power converter considering the significant improvement in increasing power density and efficiency compared with the conventional two-stage topology. It can achieve power factor correction without a large low-frequency output voltage ripple and is suitable for the traction battery charging application. Thus it is very meaningful to conduct researches on the key issues of this topology.However, several key problems are introduced cause of the features of this topology. These problems are identified as input current distortion, uncontrollable dc bus voltage when operating at light loads, zero voltage switching (ZVS) failure over the wide load range and saturation of the high-frequency transformer. The relationship between the input duty ratio restriction and the output voltage variation is studied. The effect of dead-time on the zero voltage switching is analyzed. Then the generation mechanism of the transformer saturation in the voltage-fed single-stage full-bridge converter is presented. A pseudo-continuous conduction mode (PCCM) voltage-fed single-stage APFC full-bridge battery charger based on asymmetric phase-shifted control is proposed in this paper. The setting method of the dead-time for ZVS over a wide load range has been optimized, and a novel duty ratio auto compensation strategy is proposed. At last, a prototype with the voltage-fed single-stage full-bridge topology is built to verify the effect of the proposed approach. Experimental results of the prototype indicate that:The PF of proposed converter maintains higher than 0.97 over entire output voltage range. The PF is 0.983 at the full load. Besides, the dc-bus voltage is controlled at 420Vdc. ZVS experimental results show that the optimal dead-time can be obtained from the proposed method to achieve ZVS over the entire load range. The maximum efficiency is about 93%. Meanwhile, the flux density bias has been eliminated. The innovations of this paper can be summarized as follows:(1) This paper has studied the relationship between the input duty ratio restriction and the output voltage variation. An asymmetric phase-shifted control method, which takes the input duty ratio as the prerequisite condition, is proposed then. As a result, the influence of the output voltage variation on the input duty ratio has been eliminated, and the PF would not be affected by the out voltage variation. The PF of proposed converter maintains higher than 0.97 over the wide output voltage range (45-80V).(2) A novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage APFC full-bridge topology is proposed. By connecting a freewheeling transistor in parallel with the input inductor, the PFC cell can operate in PCCM with constant duty ratio. The input current and the dc bus voltage can be regulated by the current control loop. The input duty ratio can be controlled constant at 0.3 when the load changes. The highest PF is 0.983. Meanwhile, the dc-bus voltage can be kept constant at 420V with the lightest load.(3) The effect of the current injection in the middle point of bridge leg and the dead-time scope has been studied in this paper. In consideration of the nonlinear inductance, an accurate setting method of the dead-time range for ZVS is presented. With the proposed analysis, the optimal dead-time can be selected to meet the specific requirement of the system and achieve ZVS over wide load range (3-15A) at the same time. The maximum efficiency is about 93% and the minimum efficiency is 88%.(4) The mechanism of the flux density bias in the single-stage APFC full-bridge converter is unreavelled in this paper. It is the unbalance duty cycle loss induced by the asymmetric phase-shifted control method. A novel duty ratio compensation strategy without additional sensors is proposed. The voltage-second imbalance is reduced to less than 1% using the proposed suppression strategy compared with 14% when the strategy is not used. Hence the reliabilities of the transistors and the system are improved.