Research On The Key Technology Of Multi-core Chip Design Based On High Density Computing

Electronic system design is being challenged by the high degree of integration and combinationof functionality. The restriction of volume, weight, and energy consumption is making theminimization of electronic system an challenge. CMP (chip multiprocessor), SiP (System inPackage), MEMs (Mirco-Electro Mechanical System), and NEMs (Nano-Electro MechanicalSystem),3D (Three Dimension) integration are becoming important areas of research in integratedcircuit design.The pursuit of convenience and low-carbon is making high density computing (HDC) anotherimportant research area after high performance computing (HPC). Even HPC, which used to not careabout cost, is becoming more concerned about unit space, unit power consumption, and evencomputing speed per unit investment.Based on the current development, CMP is becoming the key technology to advance HPC andHDC. This dissertation focuses on CMP design, evaluation, and optimization for the practical needsof HDC. It includes the following:(1) The concepts of parallel computing, high performance computing and multi-core computing,etc. are discussed. Using the multi-core system as the base platform, HDC is presented, along withthe main features of HDC and the primary research topics, as well as the evaluation of multi-coresystems. Basic problems in matrix operations are discussed, especially matrix decompositionmethods and complexity analysis. The thesis analyzes multi-core computation methods of parallelmatrix operation, and gives thoughts on the combination of multi-core systems and matrixoperations.(2) Based on the analysis of single chip multi-core processor structure and current research, thethesis presents the trend and typical structure of CMP: small core, big quantity, array andhierarchical clusters. It expounds the main types and basic design principles, and makes a theoreticalanalysis of parallel computation models, structure extension, and evaluation methods. The thesisproposes the concept of3D Neighbor Code and two types of coding methods to expand3D Graycode: coordinate expansion method and layer expansion method. It also analyzes the characteristicsand patterns of3D Neighbor Code, and proposes an3D NOC structure of real3D cluster structure:the3D Star Cluster (3D SC) structure. The NOC structure, node coding, and model descriptionmethod for3D SC are important contributions towards the quantitative research and analysis, forboth theoretical purpose and practical purpose.(3) This thesis designs a single-core RISC processor compatible with MIPS instruction set, andaccomplishes a4-core processor FPGA prototype design based on hierarchical AHB bus. It explores extensibility of processor structure and design method to increase total processor functionality.Multi-dimension matrix multiplication is used to verify system functionality and computation power.Experiments show that multi-core processor performance increases with the increase of matrixdimensions. This corroborates the theory of “balance must be maintained between the increase ofnumber of processors and the increase of problem scale.”(4) With the increase in number of cores, the scheduling and mapping of task are becomingevidently important. Based on the analysis of parallelization techniques and task mapping techniquesof multi-core systems, this thesis proposes a hierarchical task decomposition method and dynamictask scheduling technique based on embedded monitoring subnet. The decomposed calculation ofmatrix in same time complexity are discussed. Monitoring subnet provides data flow information, tobe used in intelligent control and processing of data flow. It also makes it possible to visualize andautomate the control process.(5) In3D NOC design, with the increase in number of nodes, route design and low powerconsumption design are the two key techniques. This thesis analyzes the fundamental issue in NOCand3D interconnection and integration, discusses3D NOC route and3D NOC low powerconsumption model, and poses methods on route analysis and low power consumption analysis.(6) To perform complicated signal processing on multi-core platforms is an engineeringproblem involving many disciplines. Based on the characteristics of parallel computing andmulti-core platforms, the thesis analyzes complexity issue of SAR signal processing, task schedulingmethods, and algorithm flow. SAR echo signal model and signal simulation algorithm are analyzed,along with echo simulation data calculation quantity and storage quantity. Several parallelcomputing and task decomposition methods on SAR echo simulation are proposed, as well as thetask and flow analysis on clustered multi-core platforms.The main innovations and contributions include:(1) Research field innovation. The concept of high density computing is proposed. High densitycomputing and multi-core computing is presented as an important research field. Multi-corecomputing, multi-core system evaluation, and multi-core system design are researched. Contributionis made to raise the research focus of multi-core system design and high-speed computing.(2) Theoretical innovation. For the first time, real3D cluster NOC structure is proposed:3DStar Cluster (3D SC) structure. The thesis also raises the concept of3D Neighbor Code, and putsforth two3D Gray Code expansion methods. The contribution is to convert the geometricconnectivity relationship of the large number of3D NOC nodes into array relationship, whichfacilitates the numerical abstraction of the geometry model. (3) Method innovation. Dynamic task scheduling technique based on embedded monitoringsubnet is proposed. This method could become the hardware foundation for the intelligentmanagement and automation control of multi-core computing. The contribution is to establish aclosed-loop system for dynamic data flow collection and control, and to enable the use of moderncontrol technique in multi-core data flow analysis and control.