Based On The Interconnect Of Parallel Adaptive Finite Element Modeling And Analysis Methods

From the birth of the first integrated circuit (IC) chip to nowadays, rapid development of integrated circuit technology has injected vast vitality to electronic information industry and promoted the flourish of computer, communications, consumer electronics and mobile internet industries in just a half century. As the integrated circuit manufacture process and IC design methodology advance, integrated circuits have been continuously upgraded. On the one hand, as the VLSI thechnology scales to nanoscale and the circuit frequency reaches gigahertz, interconnect cross-talk, IR-drop, signal delay and noise induced by the parasitic interconnect effect become more and more serious.The interconnects of integrated circuits become the key effect which affects the performance and reliability of the circuits. Therefore, the IC design methodology has experienced the revolution from the device-centric design to interconnect-centric design, and the parasitic extraction of interconnects has been the key issue in the second generation interconnect-centric IC design methodology. On the other hand, the continuous advance of manufacture process enables the miniaturization of the integrated circuits, but some manufacture processes have reached their physical limits, such that further scaling down of the technology size will result in more and more challenges in the cost and the manufacture process. Three-dimensional integrated circuit (3D IC) is a system-level architecture which implements chip stacking by using Through-silicon via (TSV) as vertical interconnections. Compared to2D ICs,3D ICs can get smaller footprint size, higher density of the devices and reduce the signal delay and the power. At the same time,3D-IC can implement homogeneous integration or heterogeneous integration by TSV.3D-IC is a promising technology to extend the Moore’s Law. Though3D IC can bring on huge improvement in IC’s electrical performance, serious thermal issue becomes the major challenge in the performance and reliability of3D IC.Considering the above significant issues, modeling and analysis methods for interconnect of integrated circuits has been proposed in this paper, including parasitic capacitance extraction of large scale and complex structure interconnect in integrated circuits and thermal analysis of3D IC with TSV vertical interconnections. In this paper, comprehensive research on layout extraction, mesh generation to fully automatic parasitic extraction of interconnects and fully automatic thermal analysis of3D IC has been conducted.Parasitic extraction is one of key techniques in very scale integrated circuit design that has been widely used to build the equivalent-circuit model of interconnects; thermal has been the major challenge in3D IC design and it is one of important research issues in EDA. Large-scale interconnects with complex multilayer structures and vertical interconnects with hundreds of TSVs bring on huge computational bottleneck of parasitic extraction and3D IC thermal analysis respectively. In this paper, a parallel adaptive finite element method is first applied to modeling and analysis method for interconnects of integrated circuits, including a parallel adaptive finite element method for capacitance extraction of large scale interconnects (ParAFEMCap) and a parallel adaptive finite element method for steady thermal analysis of3D IC (ParAFEMThermo). The proposed modeling and analysis method for interconnects can provide extremely high parallel scalability and numerical accuracy. First, the proposed ParAFEMCap and ParAFEMThermo have the potential of high parallel scalability by taking advantages of several advanced parallel techniques, such as parallel adaptive mesh refinement and dynamic load balancing. To the best of authors’knowledge, this is the first capacitance extraction and thermal analysis field solver that is able to run in parallel on hundreds of and even thousands of CPU cores. Second, based on the adaptive finite element method, the proposed ParAFEMCap and ParAFEMThermo are proved to converge to the exact solution of the electromagnetic problems and heat diffusion problem in a theoretically quasi-optimal rate. The solution precision of ParAFEMCap and ParAFEMThermo can easily be controlled by varying the threshold for the a posteriori error estimator, while the computational time can easily be reduced by increasing the number of CPU cores. Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems, while ParAFEMThermo also is an effective thermal analysis tool with high computational ability.Numerical results will demonstrate that ParAFEMCap and ParAFEMThermo have the advantages of high computational efficiency, high accuracy and high parallel scalability.