RF Chips Design For IR-UWB System Based On Cmos Technology

Since Federal Communications Commission (FCC) opened the unlicensed3.1-10.6GHz frequency spectrum in2002, great efforts has been making to harness this new resource by industries and research institutions. As this technique can achieve up to several hundred Mbps data rate in short range wireless communication environment which is much higher than other short range wireless communication systems such as Bluetooth and802.11a/b/g. But the development of the UWB isn’t so smooth going. The disagreement between Direct sequence UWB (DS-UWB) and the multi-band OFDM (MB-OFDM) UWB hindered the progress of UWB product for market. Therefore, the development of UWB technique is no more constrained by any system. The key is to reduce UWB chip cost and power consumption so that the consumer electronic markets can afford to employ the technique.This thesis focus on low power and low cost RF circuits and front-end architectures for carrier based impulse-radio UWB (IR-UWB) system. This thesis makes thorough analysis of common gate input multi-stage UWB LNA, especially in bandwidth noise figure(NF) and power consumption. By employing capacitor cross couple and c urrent reuse techniques, the proposed LNA can effectively reduce power consumption and NF. Operating in3-5GHz range, this LNA achieves peak power gain of18.8dB and minimum NF of3.4dB under7.8mW power consumption.Small size on-chip inductor with low quality factor to replace large on-chip inductor is also proposed for the UWB LNA,which helps to reduce chip area by75%without sacrificing the other performances.After careful examination of the architectures of radio frequency (RF) front-end, this paper proposes possible RF front-end for low order modulation scheme. To reduce system complexity and power consumption, coherent demodulation receiver based on limiting amplifier is proposed for monobit sampling system This receiver also employ current reuse LNA and transconductance amplifier, passive mixer to further reduce power consumption of the chip. The prototype chip fabricated in SMIC0.18um CMOS technology get400Mbps demodulation data rate under32mW power consumption, owing to proper receiver architecture and low power circuit techniques. The final coherent receiver only occupy less than1mm2chip area.In submicron technology, flicker noise suffers substantial up-conversion in voltage controlled oscillator (VCO), which greatly degrades phase noise of the VCO. This thesis presents series coupled quadrature VCO (QVCO) with source coupled capacitor to suppress the flicker noise up-conversion path. Simulation result shows15dB improvement of phase noise at10KHz offset. Measured result shows phase noise of-124dBc/Hz at1MHz offset while operating at4.8GHz, which is in accordance with simulation result. A fractional synthesizer with<1°rms phase noise is presented based on this QVCO.Finally this thesis presents a fully integrated BPSK modulation transceiver with integrated synthesizer. This RF transceiver chip consumes134.6mW power consumption for maximum data rate of300Mbps.It had also been applied into a high definition TV (HDTV) data streaming demo system with our baseband chip, showing125Mbps data rate over16meters transmission range.