High Speed Data Transmission, Signal And Power Integrity Technologies For Adaptive Optics Wavefront Processor

With the subaperture, correction units and sampling frequency of adaptiveoptics(AO) system increase, a more stringent requirement brought in datatransmission throughput and latency of wavefront processor. However, due to theexisting structure of the wavefront processing platform is a tightly coupled parallelbus-based interconnection structure which cannot achieve long distance sensor andmonitoring data transmission, and also go against large-scale expansion of AOsystem in the future. Therefore, the study of new interconnect structure, engineeringrealization of high-speed data transmission, as well as the electrical performanceimpact caused by the high-speed interconnect in wavefront processor is of greatsignificance to the development of wavefront processor in future and is also the corecontent of this thesis.Arious key aspects of the wavefront processor in data transmission werediscussed based on summarizing the previous work. Illustrates the characteristics ofthe data in each wavefront data processing unit, the data transfer there between isdivided into real-time data and non real-time data, and as a clue to analyze thelimitations of existing data transmission structure in future applications. In order tosolve the deficiencies in the existing data transfer structures, a FPGA based point topoint loosely data transfer structure is proposed. Compared with the originaltransmission structure, the new structure has a feature of smaller hardware interface,no bus contention, low propagation delay and strong noise suppression.For long-distance, high-speed and low-latency real-time image datatransmission of the wavefront processor, an image data stream based method isproposed. The corresponding fiber based custom real-time image data transferprotocol is designed, which has a characteristic of long transmission distance,low-latency and low resource consumption. The results show that the transmissionand protocol processing delay is only413.5ns, the effective transmission bandwidthis2.5Gbps, the error rate is less than10-12, and the method has been applied in theactual project.The impact of distributed and parallel bus based interconnects structure for dataexchange between the slope and reconstruction unit is discussed. Single and multi board data transfer interface are achieved, the results show that multi board datatransfer delay is only198ns, single board effective transmission bandwidth is2Gbps,the error rate is less than10-12, and signal board data transfer method has beenapplied in the actual project.Remote monitoring technology of wavefront processor has been researched, theoriginal CPCI tightly coupled based interconnect architecture has been improved.Combining gigabit data transmission and embedded systems technology, UDP andTCP/IP protocol based gigabit Ethernet remote monitoring data transfer realized. Theresults show that under the TCP/IP and UDP protocol the transmission speeds is220Mbps,600Mbps, respectively, the requirement of long distance monitoring datatransmission is met. Compared with the original scheme, the new one can achievelong-distance data exchange, and without additional protocol parsing chip, reducinghardware resource consumption, which will help the project implementation.Hybrid Field-Circuit approach which incorporated3D full-wave EM andsystem simulation is adopted to analyze the signal integrity problems in wavefrontprocessor. DOE method is introduced to analyze and optimize the high-speed seriallinks in wavefront processor, the method has been applied in the development of theactual processor board, under this method, the measure results show that thetransmission speeds up to6.25Gbps, the error rate is less than10-12, the systemrequirements is met.The sources of simultaneous switching noise in wavefront processor have beendiscussed in detail, a novel uniplanar electromagnetic band-gap structure is proposedfor suppression of simultaneous switching noise (SSN) in high-speed circuits on thisbasis. The new power plane mounted the features of spiral resonator, which cansuppress the SSN at lower and higher frequencies, respectively. Then full-wave andsystem simulation were applied to analyze the signal integrity (SI) performance. Thesimulated results display a good consistency with measured results and show theSSN suppression bandwidth is broadened from110MHz to5.97GHz under a noisesuppression margin of40dB, the SSN suppression characteristics are greatlyimproved in lower frequencies, approximately95%and160%of stopbandbandwidth improvement over the conventional UC-EBG and planar EBG powerplane is achieved, respectively, the SI of traces keep a good quality, eye open, eyeheight and jitter of SR-EBG board is281.6ps,494mV and44.5ps, respectively,which almost no distortion compared to the reference board. Most of the proposed design methods of high-speed data transmission andsignal and power integrity analysis in wavefront processor have been practicalapplied in projects; it provides a useful reference and help for the large-scaleadaptive optics wavefront processor in high-speed data transmission interconnectiondesign and engineering implementation.