Study On High-Voltage PSOI-LDMOS

Along with advancements of the semiconductor technology and large scale integrated circuits design, microelectronics industry all over the world has developed rapidly last decades. However, new problems occur as the improvement goes ahead. Nowadays, the scaling effects, such as short channel effect (SCE), have been severely degrading device performance. And Demands for high-voltage and high-frequency electronic devices is imperative. LDMOS is considered as a candidate instead of conventional devices, due to the great potential of LDMOS at the scaling effect and high-voltage&high-frequency operations.Due to high-voltage application and merits of Silicon-on-Insulator (SOI) structure, the changed SOI structure——partial Silicon-on-Insulator (PSOI)——is chosen as the basic LDMOS structure in the research. Different from SOI, the substrate of PSOI can share a part of vertical breakdown voltage and thus improve the high-voltage characteristics of devices. Therefore, PSOI-LDMOS becomes the research objective in the dissertation.First of all. the profile, fabrication processes and merits of SOI technology are introduced. The high-voltage technology is analyzed from the lateral (the RESURF effect)and vertical (enhanced dielectric field methods) direction. Various structures of SOI-LDMOSFETs are discussed in the two directions, in which the PSOI structure will be introduced. And a novel PSOI-LDMOSFET with N-type buried layer is proposed and studied in detail in the end of Chapter2.Secondly, high-voltage characteristics of the PSOI LDMOSFETs with different polarized silicon windows were studied and discussed. Because the silicon windows of different polarities belong to different device regions, the operation of PSOI LDMOSFETs is different under different polarized silicon windows. The simulation results illustrated that the optimal breakdown voltage of P-win PSOI is higher than that of N-win PSOI, while the on-resistance of P-win PSOI is lower than that of N-win PSOI.Generally speaking, the LDMOSFETs are designed with relatively large length of the drift regions, in order to achieve high breakdown voltage. However, it is well known that the devices scaling is imperative. Thus, the PSOI-LDMOS of small device dimension is explored. The results show that the parameters:the length of the field plate, the length and doping concentration of the silicon window etc. have important impact on the breakdown voltage of the device. Finally, the kink effect of PSOI is also analyzed compared with that of SOI, which shows that the kink is obviously suppressed in the PSOI structure.Finally, the previous work is summarized and extended, which points out the shortage of work and the development direction of this study in the future.