Stability Research And Driver Design Optimization Of DC-DC Converter

With the rapid development of microelectronics and semiconductor process, power management ICs have been widely used in the areas of communication network, computer and automobile electronics. In recent years, the features in high power conversion efficiency, fast load transient response, and strong load capacity of the current mode DC-DC converters have made the application become a new trend. With increasing complexity of equipment modules, the demand for greater input current is urgent. As a result, the stability problem and how to achieve the high efficiency over a wide load range have become important in the design of DC-DC switch power supply systems.With the key technologies and basic theory presented, this paper is mainly focused on the study of peak current mode DC-DC Buck converter. The optimization design of driver circuit, the stability of current loop and the loop frequency compensation have been deeply analyzed and researched, while the design method and circuit implementation are given. The main work and innovations of this dissertation are as follows.1. Due to the poor driven ability of the DC-DC converter causing by the NMOSFET power MOSFET, an improved bootstrap driver circuit is presented. A negative feedback loop is adopted to realize the accurate driving voltage. The integrated high voltage PMOS is used to replace the diode in the traditional structure, aiming to improve the driving voltage swing maximum and decrease the conduction resistance. The characteristics in high output drive capability and low static power consumption, the trigger-level-shift circuit achieves the transition from low voltage control signal to high voltage driving signal. In order to reduce the conduction loss and switching loss, a zero-crossing detector is introduced to adjust the driving voltage swing dynamically between the CCM and DCM, which realizes the high efficiency at full load range.2. According to the sub-harmonic oscillation problem in current mode DC-DC converters, an improved adaptive slope compensation circuit is proposed. Based on the slope compensation theory, a mathematical relationship of the optimal slope compensation is established with the conduction resistance introduced to derivate the duty cycle expression, and three types of this relationship applicable to Buck, Boost and Buck-Boost are presented. The test results show that the stability of the current loop is guaranteed under different duty cycle and different load conditions. For the effect of the slope compensation on load capability at high duty cycle, a summing circuit integrated sensing signal and slope signal is proposed. Based on the charge transfer characteristic of the capacitor, the proposed circuit has achieved the summing signal on the top plate of the capacitor, while the sensing current is added on the bottom. By detecting the inductor current directly and limiting the maximum value, the variation of duty cycle would have little effect on peak current and load capability. In addition, the constant current start-up circuit is presented to support the load capability during the start process. Finally, a novel adaptive slope compensation circuit is proposed to improve the effect of synchronized frequency on the stability of current loop and load capacity in multiphase application. Based on a pseudo phase-locked loop structure, the slope compensation is dynamically adjusted according to the synchronized switching frequency. The circuit is simple to implement and can be applied in any integrated synchronous switching regulators.3. For the variation of output current over a wide range, an adaptive compensation zero circuit to achieve good transient response in current-mode DC-DC buck converter is proposed. The compensation resistance of the proportional compensator is dynamically adjusted according to the different load conditions, which makes the compensation zero and crossover frequency tracking the variation of output current, and achieves the adequate system phase margin under different load conditions. As the reference to other DC-DC design, the proposed circuit is compact and simple to implement, and also reduces the pin numbers, saves the PCB area as well. Through optimization on the compensation resistance, the compensation network is almost in dependent of temperature, model and supply voltage, which improves the reliability of the schemes. To save the chip area, an improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size. Finally, a novel adaptive compensation circuit is proposed to improve the effect of the synchronized switching frequency on the system stability. Based on a pseudo phase-locked loop structure and trans-conductance linear loop, the compensation resistance is dynamically adjusted according to the synchronized switching frequency, and the optimal compensation parameter is established, which achieves the high stability and good transient response over the wide frequency range.