Harmonic Suppression And Modulation Method Research For Multilevel Grid-Side Converter In Electric Railway Traction

Single-phase three-level neutral-point-clamped (NPC) converters have been widely used in the field of industry and railway. As the grid-side converter in electric traction system, the current harmonic from converter has a negative effect on harmonic pollution and quality of power supply, cannot meet the actual demand of energy conservation and environmental protection. So, the harmonic suppression has been paid close high attention by the industry. The larger low-order harmonics will make waveform serious distortion, increase THD, and seriously affect the power quality of the traction power supply system. High-order harmonics not only influence THD, but also may lead to harmonic resonance accidents, and cause equipment burn out. High-speed electric multiple unit (EMU) lightweight is an effective way to meet the requirements for energy conservation and environmental protection, with the rapid development of the new type wide bandgap semiconductor devices application, such as SiC and GaN, makes the multilevel converter in high voltage and high-power application become more easy to implement. Power electronic transformer with multilevel converter as its key component will be adopted and widely focused to replace the bulky power frequency traction transformer in railway traction drive system. Both single-phase three-levle and cascaded H-bridge topologies are multilevel converters, have more than one capacitor in the DC-link. Capacitance voltage unbalance is a potential defects for multilevel converters, it is a key problem must to solve in multilevel converters.In order to draw a sinusoidal line current with fewer low-order harmonics. Firstly, the influences of the DC-link voltage ripple, dead-time and forward voltage drops on line current waveform are analyzed. Then, the notch filter is used to eliminate the influence of DC-link voltage ripple. A method of inject compensation components in the modulation signal is presented to compensate the effects of dead-time and forward voltage drops. The proposed dead-time compensation method has been verified by Fourier analysis, and the forward voltage drops compensation component is calculated using real-time compensation with the variation of current. Finally, a synthesize distortion compensation method of the line current waveform is proposed for the converter. It does not require any additional hardware, can reduce total harmonic distortion (THD) and low-order harmonics of the line current effectively. Finally, the effectiveness of the proposed algorithm is verified by both simulations and experiments.The reasons of high-order harmonic problems, including the neutral voltage unbalance and modulation algorithm, were analyzed in single-phase three-level converter. In order to balance DC-link neutral point voltage, on the basis of traditional single-phase three-level unipolar double-carrier-based pulse width modulation (DCBPWM), a unipolar DCBPWM with voltage offset injection (DCBPWM-VOI) was proposed for the terrible case of load imbalance. Voltage offset component is designed and calculated quantitatively in a bad load imbalance degree. On the basis of DCBPWM and single-carrier-based pulse width modulation (SCBPWM) scheme, hybrid DCBPWM and SCBPWM schemes with both unipolar and dipolar modulation modes are proposed to mitigate high-order harmonics. These two kinds of modulation schemes can effectively reduce the high-order harmonic content THD the line current.There is the problem of DC-link voltages unbalance in the cascaded H-bridge rectifiers (CHBR). In order to rapidly realize the target of solving DC-link voltages unbalance, firstly, weakness of the existing classical DC-link voltages balance control method is analyzed. Then, single-frequency carrier phase-shift PWM with voltage offset injection (SF-CPSPWM-VOI) and double-frequency carrier phase-shift PWM with voltage offset injection (DF-CPSPWM-VOI) algorithms are proposed to compensate the weakness, and these algorithms is easy to extend to multiple CHBR. Compared with the existing classical DC-link voltages balancing control scheme, the proposed SF-CPSPWM-VOI and DF-CPSPWM have a faster speed and stronger ability of DC-link voltages balancing. Finally, an arbitrary level space vector pulse width modulation (SVPWM) algorithm that has stronger commonality and ability of DC-link capacitor voltage balance is proposed. In order to obtain lower line current distortion caused by modulation algorithm, and the same switching commutation numbers for each power switching device, and not cause DC-link capacitor voltages unbalance by the modulation algorithm, an optimized vector sequence and the calculation method of the basic vector's duty-times are designed respectively.In order to verify the feasibility and effectiveness of the proposed algorithms, the low power single-phase three-level pulse rectifier prototype and the hardware-in-the-loop experiment platform based on RT-LAB for cascaded H bridge rectifier have been build and test.