Research On Low-power Multistage Amplifier For TFT-LCD IC Chip

With the increasing growth of the modern electronic display devices,TFT-LCD has become the mainstream of the liquid crystal display and the panel display technology as a result of the features such as,the high-resolution,low-power,small weight and long-life.It has been applicated in the small,moderate,and large scale electronic devices.However,low-power TFT-LCD with the charcteristics of the high integration level and high resolution urgently need the low-power multistage amplifier that can drive the large capacitive load and has a large bandwidth.Since the design of the amplifier is related to the CMOS process,it is significant for the reasearch on the design method of amplifier under the different CMOS processes.Additionally,the trade-off among the stability,bandwidth and chip area of the amplifier is dependent on the frequency compensation technique,so it is neccessary to analyze the frequency compensation techniques of the multistage amplifier.The thesis studies the lowpower multistage amplifier that is suitable for TFT-LCD IC chip.According to the features of the low-power and large capacitive load driving ability for IC chip,design methods of the multistage amplifier were studied.Based on the g_m/I_D methodology,we improved the adaptive particle swarm optimization algorithorm,then used the mono-objective APSO algorithom and multi-objective APSO algorithom to design a two-stage miller capacitor compensation amplifier and a three-stage amplifier.The distortion and sensitivity of the common source amplifier have been also studied for the g_m/I_D methodology under the short channel CMOS technology.Then we designed an impedance adaptive compensation three-stage amplifier.A low-power four-stage amplifier with the large capacitive load driving-ability was designed and verificated by chip test.Lastly,frequency compensation techniques have been also studied.Using an advanced short channel technology,a three-stage amplifier with the active-feedback miller capacitor and serial RC compensation structure was designed and post-simulated based on the layout.The novelties presented in thesis include:1.An adaptive particle swarm optimization algorithom based on g_m/I_D method has been improved.Using the mono-objective APSO algorithom and multi-objective APSO algorithom,a two-stage miller capacitor compensation amplifier and a three-stage amplifier have been designed,it is illustrated that this method can save more time for transistor circuit design and improve the accuracy of design.Additionally,it can give more design freedom among the gain,the gain-bandwidth product,noise and phase margin for the designer.2.A low-power four-stage amplifier with the large capacitive load driving-ability has been designed and verificated by the chip test.From the output of the amplifier to that of the first gain stage,an active-feedback path was formed,which introduced a low-frequency left-half-plane zero to cancel a low-frequency left-half-plane nondonminant pole.Amplifier can drive a larger capacitive load while keeping the stability.Test results verified that it improved the figure-of-merit.3.A three-stage amplifier with the active-feedback miller capacitor and serial RC compensation structure has been proposed.The serial RC structure introduced a lowfrequency left-half-plane zero to cancel a low-frequency left-half-plane non-donminant pole,which improved the phase margin.By adjusting the RC values,complexpoles and the resultant Q-value were optimized without extra power,and its gainbandwidth product was extended.