Low Power Rf Receiver Key Technologies Research And Chip Design For Wireless Sensor Network Applications

In recent years,with the rapid development of wireless communication systems,a variety of wireless communication technologies have been widely used in daily life.The wireless sensor network(WSN)based on data has a self-organizing network architecture and can be dynamically adjusted with very high reliability.Wireless sensor networks has broad application prospects,it is a hot research area of information technology.Low power consumption is increasingly becoming one of the big trends in wireless communication system.As the key to reducing power dissipation,low power transceiver technology has come up and attracted the attention of many researchers.Low-power RF transceiver technology has important theoretical significance and application value for promoting the development of wireless communication systems especially for WSN.This thesis is supported by the national natural science foundation of China(A Study of Low Power Radio Frequency Transceiver Technology)to investigate the low power RF receiver key technologies.From the view point of system design,the WSN IEEE 802.15.4 standard was analyzed.The architecture of the low power transceiver,calculation of the overall index and link budget was presented in detail,which is the base of the module design.In this thesis,in-depth research and analysis on low noise amplifier(LNA),down-conversion Mixer,complex band pass filter(CBPF),limiter,voltage control oscillator(VCO)and some other key modules have been conducted.The obtained research results are:The topologies and design methods of the wideband LNA was analyzed in detail,and a common-gate(CG)LNA with double capacitor-cross-coupling(DCCC)technique was proposed in this paper.Analysis shows that the noise calculation of the LNA containing cross-coupling topology with half equivalent circuit will bring some error.The noise figure of the CG-LNA with DCCC technique was calculated directly,without the half equivalent circuit.Theoretical analysis shows that the noise figure of this structure is significantly lower than conventional capacitive-cross-coupling CG-LNA,but the power consumption is only half of the traditional one.The designed wideband LNA consumes 1.0mA current from the 1.8V DC supply.The 3dB bandwidth is 0.5-0.95GHz with 20.7dB voltage gain,and the minimum noise figure is 2.8dB.A detailed investigation has been carried out on the narrowband LNA.As the common-source LNA with source inductance negative feedback and some other narrowband LNAs have problems in the applications,a 2.4GHz narrowband LNA with multi-gm-boosting techniques working under 1.0V DC supply was proposed.The equation of the input resistance and voltage gain was shown.This paper focuses on the noise figure analysis and calculation,and the optimization of the noise figure was introduced.The designed narrowband LNA consumes 0.9mA current from the 1.0V DC supply.The 3dB bandwidth is 2.32～2.58GHz with 22.2dB voltage gain,and the minimum noise figure is 4.35dB.The designed wideband LNA with DCCC technique was cascaded with the mixer using current bleeding technique,constituting the low power 0.5～1 GHz wideband receiver front-end for the sub-GHz bands in IEEE 802.15.4.And the designed narrowband LNA multi-gm-boosting techniques was cascaded with the mixer exploiting current reuse technique,constituting the low voltage low power 2.4GHz narrowband receiver front-end.Moreover,a low voltage low power 0.7～2.4GHz wideband receiver front-end was proposed in this paper.The proposed design and optimization method is visual,efficient and practicable.Measurement results show that the whole receiver front-end consumes 0.83mA current from the 1.0V supply.The conversion voltage gain is 25dB,and the noise figure is below 6.9dB at sub-GHz bands.While at 2.4GHz bands,the conversion voltage gain is 18.2dB,and the noise figure is below 10.2dB.The topologies and design methods of the CBPF in receiver link was analyzed in detail,and a filter design method based on poles cascade was presented to greatly simplify the circuit structure of the conventional filter circuit and reduce power consumption.The designed 4 order CBPF contains 8 differential gm cells,only half of the active Gm-C topology based on 2 order filter cell.The whole receiver link was integrated by the low voltage low power 0.7-2.4GHz wideband receiver,4 order complex BPF and limiter.The cascade of the modules,isolation between each modules and protection ring design considerations were analyzed in this paper.And the methods for reducing the impact of the bonding wires were given.Measurement results show that the performance of the receiver link can meet the requirements of WSN system.What’s more,the research and analysis on the overall index of the frequency synthesizer has also been carried out according to the wireless sensor networks IEEE 802.15.4 physical layer protocol.The system architecture of the fractional-N phase-locked loop frequency synthesizer for sub-GHz and 2.4GHz multi-bands has been designed.Then,the loop parameters were analyzed and calculated,and the system function was verified through behavioral simulation.The theory analysis and specific circuit implementation method of the two-point modulation based on the frequency synthesizer for O-QPSK was presented in this thesis.Finally,the detailed design method of low voltage and low power voltage controlled oscillator was introduced and verified by measurements.In this thesis,in-depth research on low power RF receiver key technologies for WSN applications is conducted.A variety of low power design methods have been proposed.This thesis is mainly for the receiver system chip design according to the WSN IEEE 802.15.4 standard,but the key technologies and conclusions could be applied to the other wireless systems such as IEEE 802.11,RFID,GPS and so on.