Study On Testing Methods For TSV-based Three-dimensional Integrated Circuits

Nowadays, due to the perpetual and rapid growth in CMOS technology, Moore’s Law attains to the stage of bottleneck. TSV-Based(Through Silicon Via-Based) ThreeDimensional Integrated Circuit(3D IC), which enables low delay, low power and heterogenous technology, is therefore a promising option to extend Moore’s Law.However, before mass production and entering the market, 3D ICs must overcome a series of challenges, among them, testing issue is one of the most serious problems,which is even regarded as ‘the first challenge’. There are mainly three difficulties of 3D IC test, that is, test overheating, high test cost and lack of 3D test tools or EDA softwares.In this paper, we study on testing methods for TSV-Based 3D ICs, and propose four test optimising strategies, in order to solve three difficulties of 3D IC test. The main contributions in this paper are summarized as follows:? This paper presents a thermal-driven test application scheme, so as to relieve test overheating and high test cost. Our proposed scheme is comprised of a novel scan architecture for 3D ICs, and test ordering scheme. The novel scan architecture,which is called 3D scan tree, is able to reduce test time and compress test data, thus,optimize test cost. When combining 3D scan tree with test ordering scheme, our scheme can not only reduce test cost, but also solve the problem of test overheating.? In order to overcome the difficulty of high test cost, we present a reconfigured test architecture optimizing strategy for mid-bond and post-bond test. In contrast,we consider both test time and test TSV number in test cost model. Based on the model, our optimizing strategy triggers a sharp reduction of test cost, by optimizing stack order and Test Access Mechanism(TAM) of 3D integration.? As for the difficulty of high test cost for pre-bond test, this paper presents a costeffective optimizing scheme. In the scheme, we propose an heuristic algorithm by using core partitioning strategy. Experimental results show that our scheme can effectively achieve good performance on pre-bond test cost reduction.? In order to overcome the difficulties of both high test cost and lack of 3D test tools or EDA softwares, we introduce a powerful dual-speed Automatic Test Equipment(ATE) and propose a dual-speed TAM architecture optimization, including a novel algorithm to minimize test time. Therefore, the proposed optimization sustains theopportunity for ‘killing two birds with one stone’.