Study Of Material Interface On Nano Device Based On First Principle Calculation

In the past 50 years,Moore's law has been guiding devices to scale down,and the number of transistors on a single chip has grown from the first few thousand to two billion.With the continuous innovation of transistor technology,the size of transistor is scaling,and the complexity of physical design of device is increasing.With the development of large-scale integrated circuits in the post-Moore era,many new materials and new functional devices emerging.At the same time,with the upgrading of dielectric,source/drain and channel materials technology and the innovation of lithography technology,miniaturization of devices has become possibleAs the device size continues to scaling,it will encounter some insurmountable technical bottlenecks.Reliability problems such as carrier tunneling,leakage current,bias temperature instability,and random telegraph noise are becoming more and more obvious.These problems will affect device and circuit performance.The coupling of multiple physical mechanisms in the electrical properties of nanodevices brings difficulties to experimental research.Based on these problems,we can use theoretical calculations to separate research on a single physical mechanism,which provides not only important supplements for experiments,but also provides theoretical guidance for further process optimization and device design.In particular,the structure and materials of nanodevices are becoming more and more complicated.In particular,the structure and materials of nanodevices are becoming more and more complex.The heterogeneous interface composed of different materials has become the main factor affecting device performance.One of the most common factors affecting the device performance is the defect of the transistor oxide layer and the semiconductor material interface.With the continuous reduction of the device size,the effect of the defect on the device is more prominent.According to the threshold voltage drift and capture time,the defect concentration and location distribution can be obtained when combined with a traditional physical model.However,the results are mostly dependent on the experimental environment and the device manufacturing process,especially when multiple types of device defects are coupled;it is challenging to study different defects separately in experiments.Therefore,in order to summarize the physical mechanisms of reliability problems,it is necessary to fully consider the effects of different types of defects such as impurities and vacancies from the atomic level.At the same time,in order to predict the Schottky barrier at the material interface and select an advantageous electrode material,DFT calculation combined with the Non-equilibrium Green Function(NEGF)is an indispensable theoretical support tool for Schottky barrier calculation and transport characteristic simulationRecently,Transition Metal Dichalcogenides(TMDs)have been promising as candidate channel materials for devices below 7 nm and have attracted widespread attention.Among them,MoS2 has a relatively wide bandgap,and its two-dimensional flatness is compatible with semiconductor processes,which can effectively suppress the short channel effect caused by the size reduction.These characteristics are conducive to the realization of low power consumption and high ON/OFF ratio of logic devices.MoS2-based devices have been successfully fabricated in TFET,MOSFET,and NCFET.Although TMDs logic devices have shown excellent device performance as novel nanodevices,there are still some issues that need to be solved urgently.For example,the formation of low contact resistance interfaces between source/drain electrodes and TMDs is still a considerable challenge.Besides,the defects of TMDs devices are also one of the critical problems that restrict the application of devices.The defects will cause reliability problems such as threshold voltage drift and hysteresis of the device,which in turn limits the expected performance of logic devices and integrated circuits.Studies have shown that the main cause of many reliability problems caused by defects is charge trapping and detrapping,but the microscopic process is not yet clear.It is necessary to confirm which defect type is most likely to cause charge trapping and de-trappingIn this work,based on DFT calculation,we studied the interface characteristics of MoS2-based nanodevices.First,the Schottky barrier height(SBH)modulation of the contact interface between the source/drain of the device and the TMDs are studied.Secondly,we explored the defect characteristics of the oxide layer interface and the charge trapping/detrapping process caused by the defects.Third,for some uncontrollable factors in the actual process,such as surface roughness,we explored the influence of the channel bending caused by surface roughness on the device's transport characteristics and the performance of the logic circuit.Finally,we investigated the impact of extra charges on the trap level modulation and correlated the results with the observed leakage current and device degradation/recovery phenomena in the device.First,we studied the contact interface between traditional semiconductors(Si and Ge)and MoS2,and considered the effects of crystalline orientation,surface passivation,doping level and interfacial layer.It is found that Si tends to form n-type SBH with most TMDs materials,and Si(110)is more helpful to obtain lower SBH than Si(001)and Si(1 11)surfaces.Since the work function(WF)of Ge is higher than that of Si,the contact between Ge and TMDs is more likely to form p-type SBH.It is crucial to find that the n-type SBH can be reduced by hydrogen(H)passivation,while p-type SBH can be reduced by fluorine(H)passivation.In consideration of the practical application,we doped the traditional semiconductor part and found that when the doping concentration is less than 1E21 e/cm3,the doping has little effect on the SBH.After that,we use Ge or Si as source/drain to build MoS2 based FET device.It is found that passivation of the source and drain surfaces is beneficial to increase the device ON/OFF ratio,reduce the subthreshold swing(SS)and improve the device performance.Also,the p-type Schottky contact with very low SBH can be obtained by inserting h-BN into the interface system.The reason is that the WF of Si and Ge can be significantly improved by using single-layerh-BN as the interface layer.Secondly,we investigate the charge transfer at the interface of device materials.According to Marcus charge transfer theory,we first need to obtain the information of the initial and final states of the charge transfer and the coupling constant between the two states,and then we can calculate the charge transfer rate.The method of calculating the state-state coupling constant using first-principles is introduced.We use the Si-SiO2 interface to show the state-state coupling process between the silicon valence band maximum(VBM)and the oxygen vacancy defect,and give the coupling strength value.Considering the randomness of defects in the oxide layer,we explored the scaling behavior of the state-to-state coupling with the defect distance.Compared with the scaling behavior obtained by WKB tunneling approximation,it is found that the coupling constants obtained by the two methods decrease exponentially with defect distance.But,the coupling constants are found to be higher than the WKB results.Reliability issues in field-effect transistors,including bias temperature instability(BTI),hot carrier degradation(HCD),and random telegraph noise(RTN),are all related to charge trapping processes caused by defects.Based on first principle calculations and non-harmonic approximation Marcus charge transfer theory,we provide a method for calculating charge trapping/de-trapping.Taking the MoS2-SiO2 interface as an example,the charge trapping/de-trapping rate of different types of defects in the oxide layer was explored.We found that the defect containing a single Si dangling bond is the electron trapping center,and the trapping rate is greater than the detrapping rate,which is the efficiency trapping center.And the defect containing a single O dangling bond is a relative efficiency hole trapping center.For a defect containing double Si dangling bonds are not an efficiency trapping center due to the sizeable de-trapping rate.For the actual device manufacturing process,many changes are usually introduced,such as linear edge roughness,random doping fluctuations,and surface roughness.These factors will affect the electrical performance of the device.We took MoS2 field-effect-transistor as an example to study the influence of channel bending due to interface roughness on device transport characteristics.We found that the channel bending will cause the device's ON-state current to decrease and the OFF-state current to increase.At the same time,it will also cause the device's SS value to increase.In addition,the channel bending will cause the loss of CMOS inverter gain.The above results indicate that it is vital for nanodevices to optimize the interface roughness on the atomic scale.Finally,reliability issues such as stress induced leakage current(SILC)of nanodevices are closely related to the degradation of the oxidized dielectric layer.Although there are many studies on the mechanisms behind the device recovery and device un-recovery,the research on the effects of charge on device recovery and non-recovery is very limited.Therefore,we explored the impact of extra charges on trap level modulation in detail and considered three common types of defects,including?Si-O bonds breakage,?Si-H bonds breakage,and Si-dangling bonds repassivated by hydrogen atoms.It is shown that the electron detrapping from the defect drives the trap level far away from the Si conduction band minimum(CBM),which results in observed SILC recovery in MOSFETs.More importantly,it is found that extra electrons around the defect drive the trap level closer to the Si CBM,while extra holes around the defect drive the trap level far away from the Si VBM,indicating that accumulated holes could assist leakage current recovery.Our results successfully explain the reported experimental and theoretical results:(a)high-temperature annealing is more effective for PFETs recovery than for NFETs recovery;(b)higher leakage currents were observed in NFETs than in PMOS.Moreover,our results also indicate that the impacts of extra charges could be ignorable in devices with ultra-thin oxide thickness.